Semiconductor device

1. A device, comprising:

a semiconductor fin protruding from a substrate;

a first epitaxy feature laterally surrounding a first portion of the semiconductor fin; and

a gate stack laterally surrounding a second portion of the semiconductor fin above the first portion of the semiconductor fin, wherein the second portion of the semiconductor fin has a surface roughness lower than a surface roughness of the first epitaxy feature.

2. The device of claim 1 , further comprising:

a second epitaxy feature wrapping around a top end of the semiconductor fin above both the first portion and the second portion of the semiconductor fin.

3. The device of claim 2 , wherein the first epitaxy feature has a cross-sectional profile different than a cross-sectional profile of the second epitaxy feature.

4. The device of claim 2 , wherein the gate stack comprises a gate dielectric layer and a metal gate wrapped in the gate dielectric layer, and the gate dielectric layer meets a down-slant fact of the second epitaxy feature at the semiconductor fin.

5. The device of claim 2 , further comprising:

an interlayer dielectric (ILD) layer laterally surrounding the second epitaxy feature and disposed over the gate stack.

6. The device of claim 1 , wherein the gate stack comprises a gate dielectric layer and a metal gate wrapped in the gate dielectric layer, and the gate dielectric layer meets an up-slant fact of the first epitaxy feature at the semiconductor fin.

7. The device of claim 1 , further comprising:

a dielectric liner having a lateral portion extending along the substrate and a vertical portion extending along the semiconductor fin and terminating at a down-slant facet of the first epitaxy feature.

8. The device of claim 7 , wherein the dielectric liner resembles a U-shaped pattern from a cross-sectional view, and an entirety of the U-shaped pattern is below the first epitaxy feature from the cross-sectional view.

9. A device comprising:

a semiconductor fin protruding above a substrate;

a first epitaxy structure above the substrate, the semiconductor fin extending vertically through the first epitaxy structure, wherein a sidewall of the semiconductor fin is smoother than a sidewall of the first epitaxy structure;

a gate structure above the first epitaxy structure, the semiconductor fin further extending vertically through the gate structure; and

a second epitaxy structure above the gate structure and capping a top surface of the semiconductor fin.

10. The device of claim 9 , wherein the gate structure comprises a gate dielectric layer forming an interface with the semiconductor fin and a metal gate around the gate dielectric layer, and wherein the interface formed by the gate dielectric layer and the semiconductor fin has a surface roughness lower than a surface roughness of an outer surface of the first epitaxy structure.

11. The device of claim 9 , further comprising:

a first isolation dielectric around the first epitaxy structure; and

a liner layer having a U-shaped cross-section below the first isolation dielectric.

12. The device of claim 11 , wherein the liner layer meets a down-slant facet of the first epitaxy structure at a sidewall of the semiconductor fin.

13. The device of claim 11 , further comprising:

a second isolation dielectric wrapped in the liner layer.

14. The device of claim 9 , wherein the first epitaxy structure is spaced apart from the substrate.

15. A device, comprising:

a semiconductor fin extending from a substrate, the semiconductor fin comprising a channel region, a first region below the channel region, and a second region above the channel region;

a first source/drain feature on opposite sidewalls of the first region of the semiconductor fin, wherein the first source/drain feature has a surface roughness greater than a surface roughness of the channel region of the semiconductor fin;

a gate structure above the first source/drain feature; and

a second source/drain feature on opposite sidewalls of the second region of the semiconductor fin.

16. The device of claim 15 , wherein the second source/drain feature is further on a top surface of the second region of the semiconductor fin.

17. The device of claim 15 , wherein the first source/drain feature has a cross-sectional profile different than a cross-sectional profile of the second source/drain feature.

18. The device of claim 15 , further comprising:

a liner layer having a U-shaped cross-section below the first source/drain feature; and

an isolation dielectric inlaid in the liner layer.

19. The device of claim 18 , wherein the isolation dielectric has a top surface below a bottom surface of the first source/drain feature.

20. The device of claim 15 , wherein the first source/drain feature is separated from the substrate.