Semiconductor device
Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode. The one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device.
1. A semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device, the semiconductor device comprising:
a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode;
a plurality of first resistor elements each of which includes a first electrode and a second electrode, the first electrode of each of the plurality of first resistor elements being electrically connected to the second electrode of the transistor element;
one or more external resistance terminals to which the second electrode of each of the plurality of first resistor elements is physically connected;
a first external terminal electrically connected to the first electrode of the transistor element; and
an external control terminal electrically connected with the control electrode, wherein:
the one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device, and
the plurality of first resistor elements are identical in shape in a plan view of the semiconductor device.
2. The semiconductor device according to claim 1 , wherein
in the plan view, the plurality of first resistor elements have a shape of a quadrangle having a side parallel to a direction of electrical conduction.
3. The semiconductor device according to claim 2 , wherein
in the plan view, a surface area of each of the plurality of first resistor elements is smaller than a surface area of an external connection terminal having a smallest surface area among the external connection terminals.
4. A semiconductor device which is a facedown mounting,
chip-size-package-type semiconductor device, the semiconductor device comprising:
a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode;
a plurality of first resistor elements each of which includes a first electrode and a second electrode, the first electrode of each of the plurality of first resistor elements being electrically connected to the second electrode of the transistor element;
one or more resistance electrodes to which the second electrode of each of the plurality of first resistor elements is physically connected;
one or more external resistance terminals each of which is a partial region of the one or more resistance electrodes;
a first external terminal electrically connected to the first electrode of the transistor element; and
an external control terminal electrically connected with the control electrode, wherein:
the one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device,
at least one first resistor element among the plurality of first resistor elements is physically connected with at least one resistance electrode among the one or more resistance electrodes, and
in a plan view of the semiconductor device, a region in which the at least one first resistor element and the at least one resistance electrode are physically connected has a portion overlapping with the at least one resistance electrode.