Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the same

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and composite layers located over a substrate;

wherein:

the alternating stack comprises finger regions that are laterally spaced apart from each other by a plurality of backside trenches and a staircase region that is adjoined to each of the finger regions;

the finger regions laterally extend along a first horizontal direction and are laterally spaced apart along a second horizontal direction that is perpendicular to the first horizontal direction, and the staircase region laterally extends along the second horizontal direction;

portions of each composite layer located within a respective one of the finger regions comprise a respective first electrically conductive layer and a respective active semiconductor region that has a first semiconductor surface that contacts the respective first electrically conductive layer;

portions of each composite layer located in the staircase region comprise a respective second electrically conductive layer contacting second semiconductor surfaces of a set of active semiconductor regions that are vertically spaced from the substrate by a same vertical separation distance;

a three-dimensional array of memory elements that are laterally surrounded by a respective one of the first electrically conductive layers; and

a two-dimensional array of field effect transistors that include the active semiconductor regions and gate electrodes that are configured to electrically connect or electrically inhibit each of the first electrically conductive layers from a respective one of the second electrically conductive layers.

2. The three-dimensional memory device of claim 1 , further comprising memory openings vertically extending through portions of the insulating layers and the first electrically conductive layers that are located in a respective one of the finger regions, wherein:

the three-dimensional array of memory elements comprises memory opening fill structures comprising a respective vertical semiconductor channel and a respective vertical stack of memory elements are located within a respective one of the memory openings,

wherein the first electrically conductive layers comprise word lines of the vertical stacks of memory elements.

3. The three-dimensional memory device of claim 1 , wherein each active semiconductor region of the field effect transistors contacts and has a same height along the vertical direction as a respective one of the first electrically conductive layers, and each active semiconductor region of the field effect transistors has a same width along the second horizontal direction as the respective one of the first electrically conductive layers.

4. The three-dimensional memory device of claim 1 , wherein:

the respective active semiconductor region comprises a contiguous combination of a respective channel region, a respective source region, and a respective drain region;

each interface between a source region and a channel region within each active semiconductor region comprises a vertically straight and laterally convex surface of the source region that contacts a first vertically straight and laterally concave surface of the channel region; and

each interface between a drain region and the channel region within each active semiconductor region comprises a vertically straight and laterally convex surface of the drain region that contacts a second vertically straight and laterally concave surface of the channel region.

5. The three-dimensional memory device of claim 1 , wherein the gate electrodes vertically extend through a respective vertical stack of active semiconductor regions, are laterally spaced apart along the second horizontal direction, and are laterally surrounded by a respective gate dielectric.

6. The three-dimensional memory device of claim 5 , wherein each of the gate electrodes vertically extends at least from a horizontal plane including a top surface of a topmost one of the second electrically conductive layers and at least to a horizontal plane including a bottom surface of a bottommost one of the second electrically conductive layers.

7. The three-dimensional memory device of claim 1 , wherein:

each of the gate electrodes has a pair of planar sidewalls that are parallel to the first horizontal direction;

each of the channel regions comprises a segment having a uniform width along the second horizontal direction;

each of the channel regions has a non-uniform channel length along the first horizontal direction between a respective neighboring pair of a source region and a drain region, the non-uniform channel length varying along the second horizontal direction; and

each of the gate dielectrics contacts sidewalls of at least one channel region, at least one source region, and at least one drain region, and is laterally surrounded by at least one of the semiconductor active regions.

8. The three-dimensional memory device of claim 1 , wherein:

the first electrically conductive layers and the second electrically conductive layers are free of nickel; and

the first semiconductor surfaces and the second semiconductor surfaces comprise nickel atoms at a concentration in a range from 1 part per million to 1%.