In-memory data pooling for machine learning
A method comprises a first block of memory cells to store an input array, and a second block of memory cells. Pooling circuitry is operatively coupled to the first block of memory cells to execute in-place pooling according to a function over the input array to generate an array of output values. Writing circuitry is operatively coupled to the second block to store the array of output values in the second block of memory cells. Analog sensing circuitry is coupled to the first block of memory cells to generate analog values for the input array, wherein the pooling circuitry receives the analog values as inputs to the function. The writing circuitry operatively coupled to the second block is configured to store an analog level in each cell of the second block for the array of output values.
1. A device, comprising:
a first block of memory cells to store an input array;
a second block of memory cells, the first block of memory cells and the second block of memory cells being located within separate blocks of memory cells of a memory;
pooling circuitry operatively coupled to the first block of memory cells to execute in-place pooling according to a function over the input array to generate an array of output values; and
writing circuitry operatively coupled to the second block to store the array of output values in the second block of memory cells.
2. The device of claim 1 , including
analog sensing circuitry coupled to the first block of memory cells to generate analog values for the input array, wherein the pooling circuitry receives the analog values as inputs to the function; and
the writing circuitry operatively coupled to the second block is configured to store an analog level in each cell of the second block for the array of output values.
3. The device of claim 1 , wherein
for a set of frames of cells in the input array, the function determines a maximum analog value among cells in each frame in the set of frames to generate the array of output values, where each output value in the array of output values corresponds to a frame in the set of frames, and indicates the maximum analog value among the cells in the frame in the set of frames.
4. The device of claim 1 , wherein
for a set of frames of cells in the input array, the function determines an average analog value among cells in each frame in the set of frames to generate the array of output values, where each output value in the array of output values corresponds to a frame in the set of frames, and indicates the average analog value among the cells in the frame in the set of frames.
5. The device of claim 1 , wherein
for a set of frames of cells in the input array, the function determines a minimum analog value among cells in each frame in the set of frames to generate the array of output values, where each output value in the array of output values corresponds to a frame in the set of frames, and indicates the minimum analog value among the cells in the frame in the set of frames.
6. The device of claim 1 , including address generation circuits that apply addresses for a set of frames to the first block in coordination with the pooling circuitry.
7. The device of claim 1 , wherein the writing circuitry applies a sequence of write pulses for each cell in the second block having a number of write pulses determined according to a corresponding output value in the array of output values.
8. The device of claim 1 , wherein the writing circuitry applies a sequence of write pulses for each cell in the second block having a pulse duration determined according to a corresponding output value in the array of output values.
9. The device of claim 1 , wherein the writing circuitry applies a sequence of write pulses for each cell in the second block having a tail length of a write pulse determined according to a corresponding output value in the array of output values.
10. The device of claim 1 , wherein the second block of memory cells comprise programmable resistance memory cells.
11. The device of claim 1 , wherein the second block of memory cells comprise charge storage memory cells.
12. The device of claim 1 , wherein the first and second blocks of memory cells are implemented on a single integrated circuit or multichip module under one package.
13. A method of operating a device comprising a first block of memory cells to store an input array, and a second block of memory cells, the method comprising:
executing in-place pooling according to a function over the input array to generate an array of output values; and
storing the array of output values in the second block of memory cells,
wherein the first block of memory cells and the second block of memory cells are located within separate blocks of memory cells of a memory.
14. The method of claim 13 , wherein analog sensing circuitry is coupled to the first block of memory cells to generate analog values for the input array, the method comprising:
receiving the analog values as inputs to the function; and
storing an analog level in each cell of the second block for the array of output values.
15. The method of claim 13 , comprising:
for a set of frames of cells in the input array, determining a maximum analog value among cells in each frame in the set of frames to generate the array of output values, where each output value in the array of output values corresponds to a frame in the set of frames, and indicates the maximum analog value among the cells in the frame in the set of frames.
16. The method of claim 13 , comprising:
for a set of frames of cells in the input array, determining an average analog value among cells in each frame in the set of frames to generate the array of output values, where each output value in the array of output values corresponds to a frame in the set of frames, and indicates the average analog value among the cells in the frame in the set of frames.
17. The method of claim 13 , comprising:
for a set of frames of cells in the input array, determining a minimum analog value among cells in each frame in the set of frames to generate the array of output values, where each output value in the array of output values corresponds to a frame in the set of frames, and indicates the minimum analog value among the cells in the frame in the set of frames.
18. The method of claim 13 , comprising:
applying addresses for a set of frames to the first block and the second block in coordination with said in-place pooling.
19. The method of claim 13 , comprising:
applying a sequence of write pulses for each cell in the second block having a number of write pulses determined according to a corresponding output value in the array of output values.
20. The method of claim 13 , comprising:
applying a sequence of write pulses for each cell in the second block having a pulse duration determined according to a corresponding output value in the array of output values.
21. The method of claim 13 , comprising:
applying a sequence of write pulses for each cell in the second block having a tail length of a write pulse determined according to a corresponding output value in the array of output values.