IP Library Granted Patent US 11,640,949
Granted Patent B2
US 11,640,949 · App. 17/406,091 · Granted May 2, 2023

Bonded semiconductor structure utilizing concave/convex profile design for bonding pads

Inventors: Chung-Sung Chiang (Kaohsiung, TW); Chia-Wei Liu (Tainan, TW); Yu-Ruei Chen (New Taipei, TW); Yu-Hsiang Lin (New Taipei, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L24/06H01L23/488H01L23/53228H01L25/0655
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Quick Facts
Patent No.
US 11,640,949
App. No.
17/406,091
Granted
May 2, 2023
Kind
B2
Abstract

A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height.

Claims (15)

1. A bonded semiconductor structure, comprising:

a first device wafer, comprising:

a first dielectric layer;

a first bonding pad disposed in the first dielectric layer; and

a first bonding layer on the first dielectric layer, wherein an angle between a sidewall of the first bonding layer and a top surface of the first bonding pad is larger than 90 degrees; and

a second device wafer, comprising:

a second dielectric layer;

a second bonding layer on the second dielectric layer; and

a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer, wherein a conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer comprise a step-height.

2. The bonded semiconductor structure according to claim 1 , wherein a height of the step-height and a thickness of the first bonding layer are the same.

3. The bonded semiconductor structure according to claim 1 , wherein a sidewall of the first bonding layer directly contacts a sidewall of the second bonding pad.

4. The bonded semiconductor structure according to claim 1 , wherein a thickness of the first bonding layer and a thickness of the second bonding layer are different.

5. The bonded semiconductor structure according to claim 1 , wherein the first bonding layer and the second bonding layer comprise silicon carbonitride (SiCN).

6. The bonded semiconductor structure according to claim 1 , wherein the first dielectric layer and the second dielectric layer comprise silicon oxide (SiO 2 ).

7. The bonded semiconductor structure according to claim 1 , wherein the first bonding pad and the second bonding pad comprise copper (Cu).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2021
From: CHIANG, CHUNG-SUNG; LIU, CHIA-WEI; CHEN, YU-RUEI; LIN, YU-HSIANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 057221/0479 →
Priority Claims (1)
CN 202110776523.5 · Jul 9, 2021 · national
Continuity (1)
Related Publication 20230008792A1 · Jan 12, 2023