Systems and methods to zero a tile register pair
Embodiments detailed herein relate to systems and methods to zero a tile register pair. In one example, a processor includes decode circuitry to decode a matrix pair zeroing instruction having fields for an opcode and an identifier to identify a destination matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded matrix pair zeroing instruction to zero every element of a left matrix and a right matrix of the identified destination matrix.
1. A processor comprising:
a tile storage to store a first two-dimensional tile and a second two-dimensional tile;
fetch circuitry to fetch an instruction;
decode circuitry coupled with the fetch circuitry, the decode circuitry to decode the instruction, the instruction having an opcode and indicating the first and second two-dimensional tiles; and
execution circuitry coupled with the decode circuitry and the tile storage, the execution circuitry, based on the instruction, to zero every element of the second two-dimensional tile if a parameter associated with the second two-dimensional tile has a first value.
2. The processor of claim 1 , wherein the first value is a true value.
3. The processor of claim 1 , wherein the parameter is a single bit.
4. The processor of claim 1 , wherein the parameter is one of a plurality of parameters each corresponding to a different tile of a plurality of tiles.
5. The processor of claim 1 , wherein the parameter is a single bit of a byte, and wherein each bit of the byte corresponds to a different tile of a plurality of tiles.
6. The processor of claim 1 , wherein the execution circuitry is to zero every element of the first two-dimensional tile if the parameter has the first value.
7. The processor of claim 1 , wherein the tile storage comprises a plurality of registers.
8. The processor of claim 1 , wherein the second two-dimensional tile has a configurable number of rows and columns.
9. The processor of claim 1 , further comprising a register to store a value indicative of a number of columns of the second two-dimensional tile.
10. The processor of claim 1 , wherein a number of rows of the second two-dimensional tile is based on a size of data elements of the second two-dimensional tile.
11. The processor of claim 1 , wherein the execution circuitry, to zero every element of the second two-dimensional tile, is to zero each row of elements of the second two-dimensional tile one at a time.
12. A processor comprising:
a tile storage to store a first two-dimensional tile and a second two-dimensional tile;
fetch circuitry to fetch an instruction;
decode circuitry coupled with the fetch circuitry, the decode circuitry to decode the instruction, the instruction having an opcode and indicating the first and second two-dimensional tiles; and
execution circuitry coupled with the decode circuitry and the tile storage, the execution circuitry, based on the instruction, to:
zero every element of the first two-dimensional tile if a parameter has a first value; and
zero every element of the second two-dimensional tile if the parameter has the first value.
13. The processor of claim 12 , wherein the parameter is one of a plurality of parameters including at least a second parameter corresponding to a third two-dimensional tile.
14. The processor of claim 12 , wherein the parameter is part of a byte.
15. The processor of claim 12 , wherein the tile storage comprises a plurality of registers.
16. The processor of claim 12 , wherein the second two-dimensional tile has a configurable number of rows and columns.
17. The processor of claim 12 , further comprising a register to store a value indicative of a number of columns of the second two-dimensional tile.
18. The processor of claim 12 , wherein a number of rows of the second two-dimensional tile is based on a size of data elements of the second two-dimensional tile.
19. The processor of claim 12 , wherein the execution circuitry, to zero every element of the second two-dimensional tile, is to zero each row of elements of the second two-dimensional tile one at a time.
20. A method comprising:
storing a first two-dimensional tile and a second two-dimensional tile in a tile storage;
fetching an instruction;
decoding the instruction, the instruction having an opcode and indicating the first and second two-dimensional tiles; and
executing the instruction to zero every element of the second two-dimensional tile if a parameter associated with the second two-dimensional tile has a first value.
21. The method of claim 20 , wherein the parameter is a single bit of a byte, and wherein each bit of the byte corresponds to a different tile of a plurality of tiles, and further comprising a register to store a value indicative of a number of columns of the second two-dimensional tile.
22. The method of claim 20 , further comprising zeroing every element of the first two-dimensional tile if the parameter has the first value.
23. The method of claim 20 , wherein the parameter is one of a plurality of parameters each corresponding to a different tile of a plurality of tiles, and wherein a number of rows of the second two-dimensional tile is based on a size of data elements of the second two-dimensional tile.
24. A system on a chip (SoC) comprising:
a memory controller; and
a processor core coupled with the memory controller, the processor core comprising:
a tile storage to store a first two-dimensional tile and a second two-dimensional tile;
fetch circuitry to fetch an instruction;
decode circuitry coupled with the fetch circuitry, the decode circuitry to decode the instruction, the instruction having an opcode and indicating the first and second two-dimensional tiles; and
execution circuitry coupled with the decode circuitry and the tile storage, the execution circuitry, based on the instruction, to zero every element of the second two-dimensional tile if a parameter associated with the second two-dimensional tile has a first value.
25. The SoC of claim 24 , wherein the parameter is a single bit, and wherein the parameter is one of a plurality of parameters each corresponding to a different tile of a plurality of tiles.
26. The SoC of claim 24 , wherein the execution circuitry is to zero every element of the first two-dimensional tile if the parameter has the first value.
27. The SoC of claim 24 , wherein the second two-dimensional tile has a configurable number of rows and columns, and further comprising a register to store a value indicative of a number of columns of the second two-dimensional tile.
28. A system comprising:
a system memory; and
a processor coupled with the system memory, the processor comprising:
a tile storage to store a first two-dimensional tile and a second two-dimensional tile;
fetch circuitry to fetch an instruction;
decode circuitry coupled with the fetch circuitry, the decode circuitry to decode the instruction, the instruction having an opcode and indicating the first and second two-dimensional tiles; and
execution circuitry coupled with the decode circuitry and the tile storage, the execution circuitry, based on the instruction, to zero every element of the second two-dimensional tile if a parameter associated with the second two-dimensional tile has a first value.
29. The system of claim 28 , wherein the parameter is a single bit, and wherein the parameter is one of a plurality of parameters each corresponding to a different tile of a plurality of tiles.
30. The system of claim 28 , wherein the execution circuitry is to zero every element of the first two-dimensional tile if the parameter has the first value.
31. The system of claim 28 , wherein the second two-dimensional tile has a configurable number of rows and columns, and further comprising a register to store a value indicative of a number of columns of the second two-dimensional tile.