Method for preparing a p-type semiconductor structure, enhancement mode device and method for manufacturing the same
The present application provides a method for preparing a p-type semiconductor structure, an enhancement mode device and a method for manufacturing the same. The method for preparing a p-type semiconductor structure includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer, and at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.
1. A method for preparing a p-type semiconductor structure, comprising the following steps:
preparing a p-type semiconductor layer;
preparing a protective layer on the p-type semiconductor layer, the protective layer being made of AN or AlGaN; and
annealing the p-type semiconductor layer under protection of the protective layer;
wherein at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth, and the protective layer is one of p-type doped, n-type doped, and p-type and n-type co-doped.
2. The method of claim 1 , wherein the annealing the p-type semiconductor layer under protection of the protective layer comprises:
annealing the p-type semiconductor layer under protection of the protective layer by in-situ annealing.
3. The method of claim 1 , wherein a preparation temperature of the protective layer is not higher than a preparation temperature of the p-type semiconductor layer.
4. A method for manufacturing an enhancement mode device, comprising the following steps:
forming a channel layer on a substrate;
forming a barrier layer on the channel layer;
forming a p-type semiconductor layer on the barrier layer;
forming a protective layer on the p-type semiconductor layer, the protective layer being made of AN or AlGaN, and the p-type semiconductor layer being formed between the barrier layer and the protective layer; and
annealing the p-type semiconductor layer under protection of the protective layer;
wherein at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth, and the protective layer is one of p-type doped, n-type doped, and p-type and n-type co-doped.
5. The method of claim 4 , wherein the annealing the p-type semiconductor layer under protection of the protective layer comprises:
annealing the p-type semiconductor layer under protection of the protective layer by in-situ annealing.
6. The method of claim 4 , wherein the p-type semiconductor layer comprises anyone or any combination of p-type GaN, p-type InGaN and p-type AlInGaN.
7. The method of claim 4 , wherein the p-type semiconductor layer is doped with Mg.
8. The method of claim 4 , wherein a preparation temperature of the protective layer is not higher than a preparation temperature of the p-type semiconductor layer.
9. The method of claim 4 , wherein a thin film layer is formed on the barrier layer before forming the p-type semiconductor layer on the barrier layer, and the thin film layer is one of an insulating layer and an n-type semiconductor layer.
10. The method of claim 9 , further comprising the following steps:
forming a groove in the thin film layer, the groove being located at a gate region.
11. An enhancement mode device, comprising:
a substrate;
a channel layer disposed on the substrate;
a barrier layer disposed on the channel layer;
a p-type semiconductor layer disposed on the channel layer; and
a protective layer disposed on the p-type semiconductor layer, the protective layer being made of AN or AlGaN, and the p-type semiconductor layer being located between the barrier layer and the protective layer;
wherein the p-type semiconductor layer is formed by annealing and under protection of the protective layer, at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth, and the protective layer is one of p-type doped, n-type doped, and p-type and n-type co-doped.
12. The enhancement mode device of claim 11 , wherein the p-type semiconductor layer is annealed by in-situ annealing.
13. The enhancement mode device of claim 11 , wherein the p-type semiconductor layer comprises anyone or any combination of p-type GaN, p-type InGaN and p-type AlInGaN.
14. The enhancement mode device of claim 11 , further comprising:
a thin film layer disposed between the barrier layer and the p-type semiconductor layer;
wherein the thin film layer is one of an insulating layer and an n-type semiconductor layer.
15. The enhancement mode device of claim 14 , wherein the thin film layer comprises a groove located at a gate region.
16. The enhancement mode device of claim 11 , wherein a preparation temperature of the protective layer is not higher than a preparation temperature of the p-type semiconductor layer.
17. The enhancement mode device of claim 11 , further comprising:
a source and a drain, located on the channel layer; and
a gate, located on the protective layer and between the source and the drain;
wherein the protective layer is located between the gate and the p-type semiconductor layer.