Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a via provided above a substrate, a conductive layer provided on the via, and a via provided on the conductive layer. The via, the conductive layer, and the via are one continuous structure.
1. A semiconductor memory device comprising:
a stacked body including a plurality of conductive layers stacked in a first direction;
a first pillar including a first semiconductor layer and extending in the stacked body in the first direction;
a second pillar including a second semiconductor layer and extending in the stacked body in the first direction;
a first contact plug extending in the first direction, provided above the stacked body, and electrically connected to the first semiconductor layer;
a second contact plug extending in the first direction, provided above the stacked body, and electrically connected to the second semiconductor layer;
a first charge storage layer provided between the plurality of conductive layers and the first semiconductor layer;
a second charge storage layer provided between the plurality of conductive layers and the second semiconductor layer;
a first interconnection provided above and on the first contact plug and extending in a second direction crossing the first direction;
a second interconnection provided above and on the second contact plug and extending in the second direction and arranged in a third direction of the first interconnection, the third direction crossing the first direction and the second direction;
a third contact plug provided above and on the first interconnection and extending in the first direction; and
a fourth contact plug provided above and on the second interconnection and extending in the first direction;
wherein the first contact plug, the first interconnection, and the third contact plug are made of one continuous layer,
the second contact plug, the second interconnection, and the fourth contact plug are made of one continuous layer,
the second contact plug is disposed in a position in the second direction different from the first contact plug, and
the fourth contact plug is disposed in a position in the second direction different from the third contact plug.
2. The semiconductor memory device according to claim 1 , wherein
the first contact plug and the first interconnection have no boundary region between them, and
the first interconnection and the third contact plug have no boundary region between them.
3. The semiconductor memory device according to claim 1 , wherein in the third direction intersecting the first direction and the second direction, a first width of the first interconnection at a first position is larger than a second width of the first interconnection at a second position farther from the first contact plug than the first position.
4. The semiconductor memory device according to claim 1 , wherein
the first contact plug has a columnar shape extending in the first direction, and
a first diameter of the first contact plug at a first position is larger than a second diameter of the first contact plug at a second position farther from the first interconnection than the first position.
5. The semiconductor memory device according to claim 1 , wherein
the third contact plug has a columnar shape extending in the first direction, and
a third diameter of the third contact plug at a first position is larger than a fourth diameter of the third contact plug at a second position farther from the first interconnection than the first position.
6. The semiconductor memory device according to claim 1 , wherein in the third direction intersecting the first direction and the second direction, a width of the first interconnection is larger than a diameter of the third contact plug.
7. The semiconductor memory device according to claim 1 , wherein
the plurality of conductive layers stacked in the first direction is disposed between a substrate and the first contact plug.
8. The semiconductor memory device according to claim 7 , wherein portions where the plurality of conductive layers and the first pillar intersect each other are configured to function as memory cell transistors.
9. The semiconductor memory device according to claim 8 , wherein
the first interconnection is a bit line configured to have a current flow through it from the memory cell transistors, and
the plurality of conductive layers are word lines connected to gates of the memory cell transistors.
10. The semiconductor memory device according to claim 1 , wherein a length of the first interconnection in the second direction is greater than a length of the first interconnection in the first direction.
11. A semiconductor memory device comprising:
a stacked body including a plurality of conductive layers stacked in a first direction;
a first pillar including a first semiconductor layer and extending in the stacked body in the first direction;
a second pillar including a second semiconductor layer and extending in the stacked body in the first direction;
a first contact plug, provided above the stacked body, and electrically connected to the first semiconductor layer;
a first interconnection provided above the first contact plug in the first direction, the first interconnection being provided on the first contact plug and extending in a second direction crossing the first direction; and
a second contact plug provided above the first interconnection in the first direction, the second contact plug being provided on the first interconnection;
a first charge storage layer provided between the plurality of conductive layers and the first semiconductor layer; and
a second charge storage layer provided between the plurality of conductive layers and the second semiconductor layer,
wherein in a third direction crossing the first direction and the second direction, a first width of the first interconnection at a first position is larger than a second width of the first interconnection at a second position farther from the first contact plug than the first position of the first interconnection, and
the first contact plug, the first interconnection, and the second contact plug are made of one continuous layer.
12. The semiconductor memory device according to claim 11 , wherein the first contact plug, the first interconnection, and the second contact plug are made of one continuous layer.
13. The semiconductor memory device according to claim 11 , wherein
the first contact plug and the first interconnection have no boundary region between them, and
the first interconnection and the second contact plug have no boundary region between them.
14. The semiconductor memory device according to claim 11 , wherein
the first contact plug extends in the first direction, and
the second contact plug extends in the first direction.
15. The semiconductor memory device according to claim 14 , wherein
the first contact plug has a columnar shape extending in the first direction, and
a first diameter of the first contact plug at a first position is larger than a second diameter of the first contact plug at a second position farther from the first interconnection than the first position of the first contact plug.
16. The semiconductor memory device according to claim 14 , wherein
the second contact plug has a columnar shape extending in the first direction, and
a third diameter of the second contact plug at a first position is larger than a fourth diameter of the second contact plug at a second position farther from the first interconnection than the first position of the second contact plug.
17. The semiconductor memory device according to claim 14 , wherein
the plurality of conductive layers stacked in the first direction is disposed between a substrate and the first contact plug.
18. The semiconductor memory device according to claim 17 , wherein portions where the plurality of conductive layers and the first pillar intersect each other are configured to function as memory cell transistors.
19. The semiconductor memory device according to claim 18 , wherein
the first interconnection is a bit line configured to have a current flow through it from the memory cell transistors, and
the plurality of conductive layers are word lines connected to gates of the memory cell transistors.
20. The semiconductor memory device according to claim 11 , wherein in the third direction, a width of the first interconnection is larger than a diameter of the second contact plug.