Three-dimensional memory devices and methods for forming the same
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure, comprising:
an array of NAND memory strings;
a first peripheral circuit of the array of NAND memory strings, the first peripheral circuit comprising a first transistor;
a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, the polysilicon layer being in contact with sources of the array of NAND memory strings; and
a first semiconductor layer in contact with the first transistor;
a second semiconductor structure, comprising:
a second peripheral circuit of the array of NAND memory strings, the second peripheral circuit comprising a second transistor; and
a second semiconductor layer in contact with the second transistor; and
a bonding interface between the first semiconductor structure and the second semiconductor structure,
wherein a thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer;
the second semiconductor layer is between the bonding interface and the second peripheral circuit; and
the first semiconductor layer is between the polysilicon layer and the second semiconductor layer.
2. The 3D memory device of claim 1 , wherein the first peripheral circuit is between the first semiconductor layer and the polysilicon layer.
3. The 3D memory device of claim 1 , wherein each of the first and second semiconductor layers comprises single crystalline silicon.
4. The 3D memory device of claim 1 , wherein
the first transistor comprises a first gate dielectric;
the second transistor comprises a second gate dielectric; and
a thickness of the first gate dielectric is greater than a thickness of the second gate dielectric.
5. The 3D memory device of claim 4 , wherein a difference between the thicknesses of the first and second gate dielectrics is at least 5-fold.
6. The 3D memory device of claim 4 , wherein
the first semiconductor structure further comprises a third peripheral circuit of the array of NAND memory strings, the third peripheral circuit comprising a third transistor comprising a third gate dielectric; and
the second semiconductor structure further comprises a fourth peripheral circuit of the array of NAND memory strings, the fourth peripheral circuit comprising a fourth transistor comprising a fourth gate dielectric.
7. The 3D memory device of claim 6 , wherein the third and fourth gate dielectrics have a same thickness.
8. The 3D memory device of claim 7 , wherein the thickness of the third and fourth gate dielectrics is between the thicknesses of the first and second gate dielectrics.
9. The 3D memory device of claim 6 , wherein the third and fourth peripheral circuits comprise at least one of a page buffer circuit or a logic circuit.
10. The 3D memory device of claim 1 , wherein
the first semiconductor structure further comprises a first interconnect layer between the polysilicon layer and the first transistor, the first interconnect layer comprising a first interconnect coupled to the first transistor; and
the second semiconductor structure further comprises a second interconnect layer such that the second transistor is between the second interconnect layer and the bonding interface, the second interconnect layer comprising a second interconnect coupled to the second transistor.
11. The 3D memory device of claim 10 , wherein the first interconnect comprises tungsten, and the second interconnect comprises copper.
12. The 3D memory device of claim 10 , wherein
the first semiconductor structure further comprises:
a third interconnect layer such that the array of NAND memory strings is between the third interconnect layer and the polysilicon layer, the third interconnect layer comprising a third interconnect coupled to the array of NAND memory strings;
a first contact through the polysilicon layer and coupling the third interconnect to the first interconnect; and
a second contact through the first semiconductor layer and coupled to the first interconnect; and
the second semiconductor structure further comprises a third contact through the second semiconductor layer and coupled to the second interconnect.
13. The 3D memory device of claim 1 , wherein
the first semiconductor structure further comprises a first pad-out interconnect layer above the array of NAND memory strings; or
the second semiconductor structure further comprises a second pad-out interconnect layer above the second transistor.
14. The 3D memory device of claim 1 , wherein the first peripheral circuit comprises a driving circuit, and the second peripheral circuit comprises an input/output (I/O) circuit.
15. The 3D memory device of claim 1 , further comprising:
a first voltage source coupled to the first peripheral circuit and configured to provide a first voltage to the first peripheral circuit; and
a second voltage source coupled to the second peripheral circuit and configured to provide a second voltage to the second peripheral circuit,
wherein the first voltage is greater than second first voltage.
16. The 3D memory device of claim 1 , wherein
the first semiconductor structure further comprises a first bonding layer such that the first semiconductor layer is between the first bonding layer and the first transistor, the first bonding layer comprising a first bonding contact;
the second semiconductor structure further comprises a second bonding layer such that the second semiconductor layer is between the second bonding layer and the second transistor, the second bonding layer comprising a second bonding contact; and
the first bonding contact is in contact with the second bonding contact at the bonding interface.
17. The 3D memory device of claim 1 , wherein the first transistor is formed on the first semiconductor layer, and the second transistor is formed on the second semiconductor layer.
18. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure, comprising:
an array of memory cells,
first transistors on a first semiconductor layer,
a polysilicon layer between the array of memory cells and the first transistors, and in contact with the array of memory cells; and
a second semiconductor structure bonded with the first semiconductor structure, and comprising second transistors on a second semiconductor layer,
wherein a thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer,
the second semiconductor layer is between the first transistors and the second transistors, and
the first semiconductor layer is between the polysilicon layer and the second semiconductor layer.
19. The 3D memory device of claim 18 , further comprising:
a bonding layer where the first semiconductor structure is bonded with the second semiconductor structure, and being sandwiched between the first semiconductor layer and the second semiconductor layer.
20. The 3D memory device of claim 18 , further comprising:
each first transistor comprises a first gate dielectric;
each second transistor comprises a second gate dielectric; and
wherein a thickness of the first gate dielectric is greater than a thickness of the second gate dielectric.