Semiconductor device and semiconductor module

1. A semiconductor device comprising:

a first lead frame;

a first semiconductor chip bonded to the first lead frame;

a second lead frame;

a second semiconductor chip bonded to the second lead frame; and

an inductor chip mounted on the second lead frame, the inductor chip being placed between the first semiconductor chip and the second semiconductor chip in plan view,

wherein the inductor chip comprises:

a substrate;

a lower side inductor wiring formed over the substrate;

an upper side metal wiring layer formed over the lower side inductor wiring in sectional view, the upper side metal wiring layer including inner metal wirings disposed relative to each other with even pitches and an outermost peripheral metal wiring surrounding the lower side inductor wiring and the inner metal wirings in a plan view, wherein a distance between the adjacent wirings forming the inner metal wirings being less than a distance between the outermost peripheral metal wiring and an outermost wiring of the inner metal wirings, and the outermost peripheral metal wiring is not in direct contact with the substrate;

a first insulating material formed over the substrate, the lower side inductor wiring formed within the first insulating material, the outermost peripheral metal wiring being electrically isolated from the substrate by the first insulating material;

an electrode pad formed on the outside the lower side inductor wiring in a plan view, the electrode pad capable of applying an electric potential to the lower side inductor wiring;

a contact portion formed near a central part of the lower side inductor wiring such that the contact portion is in contact with the lower side inductor wiring, the electric potential from the electrode pad being applied to the lower side inductor wiring through the contact portion; and

wherein the outermost wiring of the inner metal wirings is apart from the outermost peripheral metal wiring such that a distance is constant between the outermost wiring and the outermost peripheral metal wiring at a whole part of the outermost wiring having a curvature.

2. The semiconductor device according to claim 1 , wherein a second insulating material is disposed between the lower side inductor wiring and the upper side metal wiring layer.

3. The semiconductor device according to claim 2 , wherein a coil protective layer is placed over the upper side metal wiring layer.

4. The semiconductor device according to claim 3 , wherein the lower side inductor wiring is formed with adjacent wirings wherein the adjacent wirings of the lower side inductor wiring are disposed relative to each other with even pitches.

5. The semiconductor device according to claim 4 , wherein a wiring pattern is connected between the electrode pad and the contact portion.

6. The semiconductor device according to claim 5 , wherein the upper side metal wiring layer is made of a material including copper.

7. The semiconductor device according to claim 6 , wherein the lower side inductor wiring is made of a material including copper.

8. The semiconductor device according to claim 7 , wherein a control signal is supplied from the first semiconductor chip to the second semiconductor chip via the inductor chip.

9. The semiconductor device according to claim 8 , wherein the first semiconductor chip, the second semiconductor chip, and the inductor chip are molded and formed as a Small Outline Package (SOP) package.

10. The semiconductor device according to claim 9 , wherein the coil protective film is made of a material including a polyimide.

11. The semiconductor device according to claim 10 , wherein metal wires are connected between the first semiconductor chip and the inductor chip.

12. The semiconductor device according to claim 11 , wherein a high output voltage transistor with a high output voltage rating is formed in the second semiconductor chip, which high output voltage rating is higher than an output voltage rating of a low output voltage transistor formed in the first semiconductor chip.

13. The semiconductor device according to claim 12 , wherein size of the inductor chip is smaller than the second semiconductor chip in plan view.

14. The semiconductor device according to claim 13 , wherein size of the inductor chip is smaller than the first semiconductor chip in plan view.

15. The semiconductor device according to claim 14 , wherein the upper side metal wiring layer is formed as including a rounded shape.

16. The semiconductor device according to claim 15 , wherein the outermost peripheral metal wiring is separated from the lower side inductor wiring and the inner metal wirings electrically.

17. The semiconductor device according to claim 16 , further comprising a second wiring having an upper surface formed between the lower side inductor wiring and the substrate such that the lower surface of the outermost peripheral metal wiring is opposed to the upper surface of the second wiring and is not electrically coupled to the second wiring.

18. The semiconductor device according to claim 17 , wherein the second wiring is sandwiched between the lower side inductor wiring and substrate.

19. The semiconductor device according to claim 18 , wherein no conductive structure is disposed between the upper surface of the second wiring and the lower surface of the outermost peripheral metal wiring.

20. The semiconductor device according to claim 19 , wherein the coil protective film is thicker than a thickness of the upper side metal wiring layer.

21. The semiconductor device according to claim 20 , wherein the outermost peripheral metal wiring is a shield wiring.

22. The semiconductor device according to claim 21 , wherein the electrode pad is formed as a rectangular shape in plan view.