IP Library › Granted Patent US 12,387,868
Granted Patent B2
US 12,387,868 · App. 18/300,193 · Granted Aug 12, 2025

Semiconductor device and semiconductor module

Inventors: Kosei Osada (Kyoto, JP); Isamu Nishimura (Kyoto, JP); Tetsuya Kagawa (Kyoto, JP); Daiki Yanagishima (Kyoto, JP); Toshiyuki Ishikawa (Kyoto, JP); Michihiko Mifuji (Kyoto, JP); Satoshi Kageyama (Kyoto, JP); Nobuyuki Kasahara (Kyoto, JP)
Assignee: ROHM CO., LTD.
H01F27/288H01F27/2804H01L23/49575H01L23/5225H01L23/5227H01L23/585H01L23/645H01F2027/2819H01L23/3107H01L2224/04042H01L2224/05554H01L2224/05567H01L2224/06135H01L2224/48137H01L2224/48195H01L2224/48247H01L2224/49113H01L2224/49175H01L2924/10253H01L2924/10272H01L2924/13091H01L2924/14H01L2924/19041H01L2924/19042H01L2924/19104
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Quick Facts
Patent No.
US 12,387,868
App. No.
18/300,193
Granted
Aug 12, 2025
Kind
B2
Abstract

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Claims (31)

1. A semiconductor device comprising:

a first lead frame;

a first semiconductor chip bonded to the first lead frame; and

an inductor chip electrically connected to the first semiconductor chip, wherein

the inductor chip comprises:

a substrate;

a first insulating material disposed over the substrate in a sectional view;

a lower side inductor wiring disposed within the first insulating material;

an upper side inductor wiring disposed over the lower side inductor wiring in a sectional view;

a conductor pattern disposed outside of the lower side inductor wiring and the upper side inductor wiring in a plan view, the conductor pattern being not in direct contact with the substrate and being electrically isolated from the substrate by the first insulating material; and

a first electrode pad disposed outside of the conductor pattern in a plan view and electrically connected to the lower side inductor wiring,

a contact portion disposed such that the lower side inductor wiring is disposed between the contact portion and the first electrode pad in a plan view and electrically connected to the lower side inductor wiring.

2. The semiconductor device according to claim 1 , wherein the conductor pattern is disposed closer to the first electrode pad than the lower side inductor wiring in a plan view.

3. The semiconductor device according to claim 1 , wherein the conductor pattern is disposed closer to the first electrode pad than the upper side inductor wiring in a plan view.

4. The semiconductor device according to claim 1 , wherein the conductor pattern has an annular shape surrounding the lower side inductor wiring and the upper side inductor wiring in a plan view.

5. The semiconductor device according to claim 1 , further comprising a second insulating material disposed over the first insulating material in a sectional view,

wherein the upper side inductor wiring and the conductor pattern are disposed within the second insulating material.

6. The semiconductor device according to claim 1 , wherein the lower side inductor wiring is disposed between the contact portion and the conductor pattern in a plan view.

7. The semiconductor device according to claim 1 , wherein

the lower side inductor wiring includes first metal wirings disposed relative to each other with even pitches, and

the upper side inductor wiring includes second metal wirings disposed relative to each other with even pitches.

8. The semiconductor device according to claim 7 , wherein

a distance between adjacent first metal wirings is less than a distance between the conductor pattern and an outermost wiring of the first metal wirings, and

a distance between adjacent second metal wirings is less than a distance between the conductor pattern and an outermost wiring of the second metal wirings.

9. The semiconductor device according to claim 1 , wherein

the conductor pattern is an electrically floated metal member, and

the conductor pattern is disposed at an intermediate region between a low voltage region including the lower side inductor wiring, the first electrode pad and the contact portion, and a high voltage region including the upper side inductor wiring.

10. The semiconductor device according to claim 1 , wherein the first electrode pad is capable of applying an electric potential to the lower side inductor wiring through the contact portion.

11. The semiconductor device according to claim 1 , further comprising:

a second lead frame; and

a second semiconductor chip bonded to the second lead frame and electrically connected to the inductor chip.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2023
From: OSADA, KOSEI; NISHIMURA, ISAMU; KAGAWA, TETSUYA; YANAGISHIMA, DAIKI; ISHIKAWA, TOSHIYUKI; MIFUJI, MICHIHIKO; KAGEYAMA, SATOSHI; KASAHARA, NOBUYUKI
To: ROHM CO., LTD.
Reel/Frame 063321/0886 →
Priority Claims (4)
JP 2013-235190 · Nov 13, 2013 · national
JP 2013-235191 · Nov 13, 2013 · national
JP 2014-145041 · Jul 15, 2014 · national
JP 2014-219492 · Oct 28, 2014 · national
Continuity (5)
Continuation 17230356 · Apr 14, 2021
Continuation 16803522 · Feb 27, 2020
Continuation 15624205 · Jun 15, 2017
Continuation 14537234 · Nov 10, 2014
Related Publication 20230298805A1 · Sep 21, 2023
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