Semiconductor package for improving bonding reliability

1. A semiconductor package comprising:

a first semiconductor chip;

a second semiconductor chip arranged above the first semiconductor chip; and

main pad structures and dummy pad structures between the first semiconductor chip and the second semiconductor chip,

wherein the main pad structures comprise first main pad structures apart from one another on the first semiconductor chip and second main pad structures apart from one another on the second semiconductor chip and bonded to the first main pad structures,

wherein the dummy pad structures comprise first dummy pad structures comprising first dummy pads that are arranged apart from one another on the first semiconductor chip and first dummy capping layers arranged on the first dummy pads, and second dummy pad structures comprising second dummy pads that are arranged apart from one another on the second semiconductor chip and second dummy capping layers arranged on the second dummy pads, and

wherein the first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.

2. The semiconductor package of claim 1 , wherein the first dummy pads and the second dummy pads comprise materials different from those of the first dummy capping layers and the second dummy capping layers.

3. The semiconductor package of claim 1 ,

wherein a first bonding insulating layer insulating the first dummy pads is further formed on the first semiconductor chip, the second dummy capping layers are bonded to the first bonding insulating layer,

wherein a second bonding insulating layer configured to insulate the second dummy pad structures is further formed on the second semiconductor chip, and

wherein the first dummy capping layers are not bonded to the second bonding insulating layer.

4. The semiconductor package of claim 1 ,

wherein each of the first dummy pad structures on the first semiconductor chip is configured to have a top width and a bottom width equal to each other, and

wherein each of the second dummy pad structures on the second semiconductor chip is configured to have a top width and a bottom width equal to each other.

5. The semiconductor package of claim 1 ,

wherein the first semiconductor chip comprises an uppermost portion including a first wiring layer, the first wiring layer is connected to the first dummy pad structures,

wherein the second semiconductor chip comprises an uppermost portion including a second wiring layer, and

wherein the second wiring layer is connected to the second dummy pad structures.

6. The semiconductor package of claim 1 ,

wherein the main pad structures are arranged in center regions of the first semiconductor chip and the second semiconductor chip in a plan view, and

wherein the dummy pad structures are arranged to surround the main pad structures in peripheral regions of the first semiconductor chip and the second semiconductor chip.

7. The semiconductor package of claim 1 ,

wherein the main pad structures are arranged in left and right regions of the first semiconductor chip and the second semiconductor chip in a plan view, and

wherein the dummy pad structures are arranged in a middle region between the left and right regions of the first semiconductor chip and the second semiconductor chip in the plan view.

8. The semiconductor package of claim 1 ,

wherein each of the first dummy pad structures is formed as a hollow pattern having an inner area from a plan view,

wherein each of the second dummy pad structures is formed as a solid pattern in the inner area of the hollow pattern included in each of the first dummy pad structures, and

wherein in the plan view, the hollow pattern and the solid pattern do not overlap.

9. The semiconductor package of claim 1 , wherein the first dummy pad structures are arranged apart from one another in a plan view on the first semiconductor chip, the second dummy pad structures are apart from one another in the plan view on the second semiconductor chip and arranged between the first dummy pad structures, and the first dummy pad structures do not overlap with the second dummy pad structures in the plan view.

10. The semiconductor package of claim 1 , wherein the first dummy pad structures and the second dummy pad structures are configured in polygonal patterns.

11. The semiconductor package of claim 1 , wherein the first dummy pad structures and the second dummy pad structures are configured in linear patterns.

12. The semiconductor package of claim 1 ,

wherein the main pad structures are arranged in at least one region of left, right, upper, and lower portions of the first semiconductor chip and the second semiconductor chip in a plan view, and

wherein the dummy pad structures are in regions in which the main pad structures are not arranged in at least one of the left, right, upper, and lower portions of the first semiconductor chip and the second semiconductor chip in the plan view.

13. A semiconductor package comprising:

a first semiconductor chip;

a second semiconductor chip arranged on the first semiconductor chip; and

main pad structures and dummy pad structures between the first semiconductor chip and the second semiconductor chip,

wherein the main pad structures comprise:

first main pad structures comprising first main pads apart from one another on the first semiconductor chip and first main capping layers on the first main pads, and

second main pad structures comprising second main pads apart from one another on the second semiconductor chip and second main capping layers on the second main pads,

wherein the first main capping layers of the first main pad structures are bonded to the second main capping layers of the second main pad structures,

wherein the dummy pad structures comprise first dummy pad structures comprising first dummy pads placed apart from one another on the first semiconductor chip and first dummy capping layers placed on the first dummy pads, and second dummy pad structures comprising second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads, and

wherein the first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.

14. The semiconductor package of claim 13 , wherein the first main pads comprise a material different from that of the first main capping layers, the second main pads comprise a material different from that of the second main capping layers, the first dummy pads comprise a material different from that of the first dummy capping layers, and the second dummy pads comprise a material different from that of the second dummy capping layers.

15. The semiconductor package of claim 13 ,

wherein each of the first main pad structures on the first semiconductor chip is configured to have a top width and a bottom width equal to each other, and

wherein each of the second main pad structures on the second semiconductor chip is configured to have a top width and a bottom width equal to each other.

16. The semiconductor package of claim 13 , wherein a width of each of the first main pad structures and the second main pad structures is greater than a width of each of the first dummy pad structures and greater than a width of each of the second dummy pad structures.

17. The semiconductor package of claim 13 , wherein the first main capping layers of the first main pad structures and the second main capping layers of the second main pad structures partially overlap and are bonded to each other in a plan view.

18. A semiconductor package comprising:

a first semiconductor chip;

a second semiconductor chip arranged on the first semiconductor chip;

main pad structures and dummy pad structures between the first semiconductor chip and the second semiconductor chip; and

bonding insulating layers between the first semiconductor chip and the second semiconductor chip and insulating the main pad structures and the dummy pad structures,

wherein the main pad structures comprise:

first main pad structures comprising first main pads placed apart from one another on the first semiconductor chip and first main capping layers on the first main pads, and

second main pad structures comprising second main pads placed apart from one another on the second semiconductor chip and second main capping layers on the second main pads,

wherein the first main capping layers of the first main pad structures are bonded to the second main capping layers of the second main pad structures,

wherein the dummy pad structures comprise:

first dummy pad structures comprising first dummy pads placed apart from one another on the first semiconductor chip and first dummy capping layers placed on the first dummy pads, and

second dummy pad structures comprising second dummy pads placed apart from one another on the second semiconductor chip and second dummy capping layers placed on the second dummy pads, and

wherein the bonding insulating layers comprise:

on the first semiconductor chip, a first bonding insulating layer insulating the first main pad structures and the first dummy pad structures, and

on the second semiconductor chip, a second bonding insulating layer insulating the second main pad structures and the second dummy pad structures,

wherein the second dummy capping layers are bonded to the first bonding insulating layer, and the first dummy capping layers are bonded to the second bonding insulating layer.

19. The semiconductor package of claim 18 ,

wherein each of the first dummy pad structures is configured to have a top width and a bottom width equal to each other, and

wherein each of the second dummy pad structures is configured to have a top width and a bottom width equal to each other.

20. The semiconductor package of claim 18 , wherein the first dummy capping layers and the second dummy capping layers comprise a material different from that of the first dummy pads and the second dummy pads.