Semiconductor package including stacked semiconductor chips
A semiconductor package including: a base layer; and a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including first to fourth semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack, and first and second chip identification pads for identifying the first to fourth semiconductor chips in each of the first and second chip stacks.
1. A semiconductor package comprising:
a base layer; and
a first chip stack and a second chip stack sequentially stacked over the base layer,
wherein each of the first and second chip stacks include first to fourth semiconductor chips which are offset stacked to expose chip pads at one side edge of each of the first to fourth semiconductor chips,
wherein the chip pads include:
stack identification pads for identifying the first chip stack and the second chip stack, and
first and second chip identification pads for identifying the first to fourth semiconductor chips in each of the first and second chip stacks,
wherein:
power is applied to the stack identification pads of the first to fourth semiconductor chips of one of the first and second chip stacks,
in the first chip stack,
the power is applied to:
the first and second chip identification pads of the first semiconductor chip,
one of the first and second chip identification pads of the second semiconductor chip, and
the other of the first and second chip identification pads of the third semiconductor chip, and
in the second chip stack,
the power is applied to:
the first and second chip identification pads of the first semiconductor chip,
one of the first and second chip identification pads of the second semiconductor chip, and
the other of the first and second chip identification pads of the third semiconductor chip.
2. The semiconductor package according to claim 1 , further comprising:
an inter-chip wire connecting the stack identification pads to which the power is applied to each other; and
a stack wire connecting the stack identification pad to which the power is applied of the first semiconductor chip to the base layer.
3. The semiconductor package according to claim 1 , wherein the power is applied to the stack identification pads of the first to fourth semiconductor chips of the first chip stack.
4. The semiconductor package according to claim 1 , wherein, in at least one of the first chip stack and the second chip stack, the power is applied to the first chip identification pad of the second semiconductor chip and the second chip identification pad of the third semiconductor chip,
the semiconductor package further comprising:
an inter-chip wire connecting the second chip identification pad of the third semiconductor chip, the first chip identification pad of the second semiconductor chip, and the first chip identification pad of the first semiconductor chip; and
a stack wire connecting the first and second chip identification pads of the first semiconductor chip to the base layer.
5. The semiconductor package according to claim 1 , wherein, in at least one of the first chip stack and the second chip stack, the power is applied to the second chip identification pad of the second semiconductor chip and the first chip identification pad of the third semiconductor chip,
the semiconductor package further comprising:
an inter-chip wire connecting the first chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip; and
a stack wire connecting the first and second chip identification pads of the first semiconductor chip to the base layer.
6. The semiconductor package according to claim 1 , wherein, remaining ones of the stack identification pads and the first and second chip identification pads, that are not power-applied ones of the stack identification pads and the first and second chip identification pads, are in a floating state.
7. The semiconductor package according to claim 6 , wherein the stack identification pads, and the first and second chip identification pads, which are in the floating state, are not connected to a wire.
8. The semiconductor package according to claim 1 , wherein the stack identification pads are aligned with each other along an offset direction,
the first chip identification pads are aligned with each other along the offset direction, and
the second chip identification pads are aligned with each other along the offset direction.
9. The semiconductor package according to claim 1 , wherein one side surface of the first semiconductor chip located at a lowermost portion of the second chip stack protrudes in a direction opposite to the offset direction farther than one side surface of the fourth semiconductor chip located at an uppermost portion of the first chip stack.
10. A semiconductor package comprising:
a base layer; and
a first chip stack and a second chip stack sequentially stacked over the base layer,
wherein each of the first and second chip stacks include first to eighth semiconductor chips which are offset stacked to expose chip pads at one side edge of each of the first to eighth semiconductor chips,
wherein the chip pads include:
stack identification pads for identifying the first chip stack and the second chip stack, and
first to third chip identification pads for identifying the first to eighth semiconductor chips in each of the first and second chip stacks,
wherein:
power is applied to the stack identification pads of the first to eighth semiconductor chips of one of the first and second chip stacks,
in the first chip stack,
the power is applied to:
the first to third chip identification pads of the first semiconductor chip,
two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and
one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips,
where the selected two of the second semiconductor chip, the selected two of the third semiconductor chip, and the selected two of the fourth semiconductor chip are different from each other, and
the selected one of the fifth semiconductor chip, the selected one of the sixth semiconductor chip, and the selected one of the seventh semiconductor chip are different from each other, and
in the second chip stack,
the power is applied to:
the first to third chip identification pads of the first semiconductor chip,
two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and
one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips,
where the selected two of the second semiconductor chip, the selected two of the third semiconductor chip, and the selected two of the fourth semiconductor chip are different from each other, and
the selected one of the fifth semiconductor chip, the selected one of the sixth semiconductor chip, and the selected one of the seventh semiconductor chip are different from each other.
11. The semiconductor package according to claim 10 , further comprising:
an inter-chip wire connecting the stack identification pads to which the power is applied to each other; and
a stack wire connecting the stack identification pad to which the power is applied of the first semiconductor chip to the base layer.
12. The semiconductor package according to claim 10 , wherein the power is applied to the stack identification pads of the first to eighth semiconductor chips of the first chip stack.
13. The semiconductor package according to claim 10 , wherein, the power is applied to the first and second chip identification pads of the second semiconductor chip, the first and third chip identification pads of the third semiconductor chip, the second and third chip identification pads of the fourth semiconductor chip, the third chip identification pad of the fifth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, and the first chip identification pad of the seventh semiconductor chip in at least one of the first chip stack and the second chip stack,
the semiconductor package further comprising:
an inter-chip wire connecting the first chip identification pad of the seventh semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the third chip identification pad of the fifth semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the first chip identification pad of the third semiconductor chip, the first chip identification pad of the second semiconductor chip, and the first chip identification pad of the first semiconductor chip, and connecting the third chip identification pad of the fourth semiconductor chip, the third chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip; and
a stack wire connecting the first to third chip identification pads of the first semiconductor chip to the base layer.
14. The semiconductor package according to claim 10 , wherein, the power is applied to the second and third chip identification pads of the second semiconductor chip, the first and third chip identification pads of the third semiconductor chip, the first and second chip identification pads of the fourth semiconductor chip, the third chip identification pad of the fifth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, and the first chip identification pad of the seventh semiconductor chip in at least one of the first chip stack and the second chip stack,
the semiconductor package further comprising:
an inter-chip wire connecting the first chip identification pad of the seventh semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the third chip identification pad of the fifth semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the third chip identification pad of the third semiconductor chip, the third chip identification pad of the second semiconductor chip, and the third chip identification pad of the first semiconductor chip, and connecting the first chip identification pad of the fourth semiconductor chip, the first chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip; and
a stack wire connecting the first to third chip identification pads of the first semiconductor chip to the base layer.
15. The semiconductor package according to claim 10 , wherein, the power is applied to the second and third chip identification pads of the second semiconductor chip, the first and third chip identification pads of the third semiconductor chip, the first and second chip identification pads of the fourth semiconductor chip, the first chip identification pad of the fifth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, and the third chip identification pad of the seventh semiconductor chip in at least one of the first chip stack and the second chip stack,
the semiconductor package further comprising:
an inter-chip wire connecting the third chip identification pad of the seventh semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the first chip identification pad of the fifth semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the third chip identification pad of the third semiconductor chip, the third chip identification pad of the second semiconductor chip, and the third chip identification pad of the first semiconductor chip, and connecting the first chip identification pad of the fourth semiconductor chip, the first chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip; and
a stack wire connecting the first to third chip identification pads of the first semiconductor chip to the base layer.
16. The semiconductor package according to claim 10 , wherein, the power is applied to the first and second chip identification pads of the second semiconductor chip, the first and third chip identification pads of the third semiconductor chip, the second and third chip identification pads of the fourth semiconductor chip, the first chip identification pad of the fifth semiconductor chip, the second chip identification pad of the sixth semiconductor chip, and the third chip identification pad of the seventh semiconductor chip in at least one of the first chip stack and the second chip stack,
the semiconductor package further comprising:
an inter-chip wire connecting the third chip identification pad of the seventh semiconductor chip, the second chip identification pad of the sixth semiconductor chip, the first chip identification pad of the fifth semiconductor chip, the second chip identification pad of the fourth semiconductor chip, the first chip identification pad of the third semiconductor chip, the first chip identification pad of the second semiconductor chip, and the first chip identification pad of the first semiconductor chip, and connects the third chip identification pad of the fourth semiconductor chip, the third chip identification pad of the third semiconductor chip, the second chip identification pad of the second semiconductor chip, and the second chip identification pad of the first semiconductor chip; and
a stack wire connecting the first to third chip identification pads of the first semiconductor chip to the base layer.
17. The semiconductor package according to claim 10 , wherein, remaining ones of the stack identification pads and the first to third chip identification pads, that are not power-applied ones of the stack identification pads and the first to third chip identification pads, are in a floating state.
18. The semiconductor package according to claim 17 , wherein the stack identification pads, and the first to third chip identification pads, which are in the floating state, are not connected to a wire.
19. The semiconductor package according to claim 10 , wherein the stack identification pads are aligned with each other along an offset direction,
the first chip identification pads are aligned with each other along the offset direction,
the second chip identification pads are aligned with each other along the offset direction, and
the third chip identification pads are aligned with each other along the offset direction.
20. The semiconductor package according to claim 10 , wherein one side surface adjacent to the chip pads of the first semiconductor chip of the second chip stack protrudes toward a direction opposite to an offset direction than one side surface adjacent to the chip pads of the eighth semiconductor chip of the first chip stack.