III-V semiconductor device with integrated power transistor and start-up circuit
A III-nitride semiconductor based heterojunction power device including: a first heterojunction transistor formed on a substrate, and a second heterojunction transistor formed on the substrate. One of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor. The enhancement mode transistor acts as a main power switch, and the depletion mode transistor acts as a start-up component.
1. A III-nitride semiconductor based heterojunction power device, comprising:
a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising:
a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least a first two dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the first III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region;
a first highly doped semiconductor region of a first conductivity type formed over the first III-nitride semiconductor region, and between the first terminal and the second terminal;
a first gate region being formed over the first highly doped semiconductor region, and between the first terminal and the second terminal; and
a second heterojunction transistor formed on the substrate, the second heterojunction transistor comprising:
a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least a second two dimensional carrier gas of the second conductivity type;
a third terminal operatively connected to the second III-nitride semiconductor region;
a fourth terminal operatively connected to the second III-nitride semiconductor region, wherein within an active area of the second heterojunction transistor the fourth terminal is laterally spaced from the third terminal in a first dimension;
a second plurality of highly doped semiconductor regions of the first conductivity type formed over the second III-nitride semiconductor region, the second plurality of highly doped semiconductor regions being formed between the third terminal and the fourth terminal, wherein the second plurality of highly doped semiconductor regions comprises at least two highly doped semiconductor regions of the first conductivity type in contact with the second III-nitride semiconductor region and laterally spaced from each other in a second dimension that is perpendicular to the first dimension;
a second gate region operatively connected to the first plurality of highly doped semiconductor regions, and
wherein one of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor.
2. The III-nitride semiconductor based heterojunction power device according to claim 1 , wherein the first heterojunction of the first III-nitride semiconductor region comprises:
a first III-nitride semiconductor layer having a first band gap formed over the substrate;
a second III-nitride semiconductor layer having a second bandgap different from the first band gap disposed on the first III-nitride semiconductor layer; and
at least the first two-dimensional carrier gas of the second conductivity type formed at an interface between the first III-nitride semiconductor layer and the second III-nitride semiconductor layer to provide a channel; and
wherein the second heterojunction of the second III-nitride semiconductor region comprises:
a third III-nitride semiconductor layer having a third band gap formed over the substrate;
a fourth III-nitride semiconductor layer having a fourth bandgap different from the third band gap disposed on the third III-nitride semiconductor layer; and
at least the second two-dimensional carrier gas of the second conductivity type formed at an interface between the third III-nitride semiconductor layer and the fourth III-nitride semiconductor layer to provide a channel.
3. The III-nitride semiconductor based heterojunction power device according to claim 2 , wherein the first III-nitride semiconductor layer, the second III-nitride semiconductor layer, the third III-nitride semiconductor layer, and the fourth III-nitride semiconductor layer each comprise any one of gallium nitride (GaN), aluminium gallium nitride (AlGaN) and indium aluminium gallium nitride (InAlGaN), and wherein at least the first two dimensional carrier gas and at least the second two dimensional carrier gas are two dimensional electron gases (2DEG) or two dimensional hole gases (2DHG).
4. The III-nitride semiconductor based heterojunction power device according to claim 1 , wherein the first heterojunction transistor is configured as the enhancement mode field effect transistor, operating as a power switch and wherein the second heterojunction transistor is configured as the depletion mode field effect transistor operating as a start-up device.
5. The III-nitride semiconductor based heterojunction power device according to claim 1 , wherein the second gate region comprises a Schottky contact or an Ohmic contact.
6. The III-nitride semiconductor based heterojunction power device according to claim 1 , wherein the first heterojunction transistor and the second heterojunction transistor are monolithically integrated within the III-nitride semiconductor based heterojunction power device.
7. The III-nitride semiconductor based heterojunction power device according to claim 1 , further comprising an isolation structure formed between the first heterojunction transistor and the second heterojunction transistor.
8. The III-nitride semiconductor based heterojunction power device according to claim 1 , wherein the second terminal and the fourth terminal are operatively connected.
9. The III-nitride semiconductor based heterojunction power device according to claim 8 , wherein the second terminal and the fourth terminal are configured as a self-isolating structure.
10. The III-nitride semiconductor based heterojunction power device according to claim 1 , wherein the first terminal is operatively connected to the second gate region.
11. The III-nitride semiconductor based heterojunction power device according to claim 1 , wherein the second heterojunction transistor is configured as a diode, with the third terminal connected to the second gate region.
12. The III-nitride semiconductor based heterojunction power device according to claim 11 , wherein the diode is connected in an anti-parallel configuration to the first heterojunction transistor and where the first terminal is connected to the third terminal and the second terminal is connected to fourth terminal.
13. A circuit, comprising:
at least two III-nitride semiconductor based heterojunction power devices arranged in a half bridge configuration, each of the at least two III-nitride semiconductor based heterojunction power devices, comprising:
a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising:
a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least a first two dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the first III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region;
a first highly doped semiconductor region of a first conductivity type formed over the first III-nitride semiconductor region, and between the first terminal and the second terminal;
a first gate region being formed over the first highly doped semiconductor region, and between the first terminal and the second terminal; and
a second heterojunction transistor formed on the substrate, the second heterojunction transistor comprising:
a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least a second two dimensional carrier gas of the second conductivity type;
a third terminal operatively connected to the second III-nitride semiconductor region;
a fourth terminal operatively connected to the second III-nitride semiconductor region, wherein within an active area of the second heterojunction transistor the fourth terminal is laterally spaced from the third terminal in a first dimension:
a second plurality of highly doped semiconductor regions of a first conductivity type formed over the second III-nitride semiconductor region, the second plurality of highly doped semiconductor regions being formed between the third terminal and the fourth terminal, wherein the second plurality of highly doped semiconductor regions comprises at least two highly doped semiconductor regions of the first conductivity type in contact with the second III-nitride semiconductor region and laterally spaced from each other in a second dimension that is perpendicular to the first dimension:
a second gate region operatively connected to the first plurality of highly doped semiconductor regions,
wherein one of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor;
wherein the second heterojunction transistor is configured as a diode, with the third terminal connected to the second gate region, and
wherein the diode is connected in an anti-parallel configuration to the first heterojunction transistor and where the first terminal is connected to the third terminal and the second terminal is connected to fourth terminal.
14. A method of manufacturing a III-nitride semiconductor based heterojunction power device, the method comprising:
forming a first III-nitride semiconductor region over a substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least a first two-dimensional carrier gas of a second conductivity type;
forming a first terminal operatively connected to the first III-nitride semiconductor region;
forming a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; and
forming a first highly doped semiconductor region of a first conductivity type formed over the first III-nitride semiconductor region, and between the first terminal and the second terminal;
forming a first gate region being formed over the first highly doped semiconductor region, and between the first terminal and the second terminal;
forming a second III-nitride semiconductor region over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least a second two-dimensional carrier gas of the second conductivity type;
forming a third terminal operatively connected to the second III-nitride semiconductor region;
forming a fourth terminal operatively connected to the second III-nitride semiconductor region, wherein within an active area of the second heterojunction transistor the fourth terminal is laterally spaced from the third terminal in a first dimension;
forming a second plurality of highly doped semiconductor regions of the first conductivity type over the second III-nitride semiconductor region, the second plurality of highly doped semiconductor regions being formed between the third terminal and the fourth terminal, wherein the second plurality of highly doped semiconductor regions comprises at least two highly doped semiconductor regions of the first conductivity type in contact with the second III-nitride semiconductor region and laterally spaced from each other in a second dimension that is perpendicular to the first dimension; and
forming a second gate region operatively connected to the second plurality of highly doped semiconductor regions, and
wherein one of the first heterojunction transistor and the second heterojunction transistors is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistors is a depletion mode field effect transistor.
15. A circuit comprising:
one or more III-nitride semiconductor based heterojunction power devices, wherein each of the one or more III-nitride semiconductor based heterojunction power device comprises:
a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising:
a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least a first two dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the first III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region;
a first highly doped semiconductor region of a first conductivity type formed over the first III-nitride semiconductor region, and between the first terminal and the second terminal;
a first gate region being formed over the first highly doped semiconductor region, and between the first terminal and the second terminal; and
a second heterojunction transistor formed on the substrate, the second heterojunction transistor comprising:
a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least a second two dimensional carrier gas of the second conductivity type;
a third terminal operatively connected to the second III-nitride semiconductor region;
a fourth terminal operatively connected to the second III-nitride semiconductor region, wherein within an active area of the second heterojunction transistor the fourth terminal is laterally spaced from the third terminal in a first dimension;
a second plurality of highly doped semiconductor regions of a first conductivity type formed over the second III-nitride semiconductor region, the second plurality of highly doped semiconductor regions being formed between the third terminal and the fourth terminal, wherein the second plurality of highly doped semiconductor regions comprises at least two highly doped semiconductor regions of the first conductivity type in contact with the second III-nitride semiconductor region and laterally spaced from each other in a second dimension that is perpendicular to the first dimension; and
a second gate region operatively connected to the first plurality of highly doped semiconductor regions, and
wherein one of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor.
16. The circuit according to claim 15 , said circuit further comprising a capacitor electrically connected to the third terminal.
17. The circuit according to claim 15 , wherein the one or more III-nitride semiconductor based heterojunction power devices comprise a plurality of III-nitride semiconductor based heterojunction power devices.
18. The circuit according to claim 15 , wherein the one or more III-nitride semiconductor based heterojunction power devices comprise a first III-nitride semiconductor based heterojunction power device and a second semiconductor based heterojunction power device arranged in a half bridge configuration.