Network transceiver with VGA channel specific equalization

1. A network transceiver device, comprising:

a plurality of variable gain amplifiers (VGAs) configured to amplify received signals;

at least two sets of analog digital converters (ADCs), each set including a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs, wherein a first set of the at least two sets of ADCs is arranged in at least a first VGA-specific channel and a second set of the at least two sets of ADCs is arranged in at least a second VGA-specific channel; and

a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive a respective output of a corresponding ADC of the at least two sets of ADCs in either the first VGA-specific channel or the second VGA-specific channel, each FFE being configured to adaptively equalize the output received from the corresponding ADC utilizing a plurality of equalization coefficients, the plurality of equalization coefficients including a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for the first VGA-specific channel and a second set of coefficient values for the second VGA-specific channel, the first and second set of coefficient values being computed independently of each other.

2. The network transceiver device of claim 1 , comprising:

a Continuous Time Linear Equalizer (CTLE) coupled on an input side of the plurality of the VGAs.

3. The network transceiver device of claim 1 , comprising:

a plurality of decision feedback equalizers (DFEs), each DFE being coupled to receive a respective output of a corresponding one of the plurality of FFEs in either the first VGA-specific channel or the second VGA-specific channel.

4. The network transceiver device of claim 3 , comprising:

a maximum likelihood sequence estimation (MLSE) equalizer coupled on an output side of the plurality of the DFEs, the MLSE equalizer being configured to correct DFE burst errors in each of the plurality of DFEs.

5. The network transceiver device of claim 1 , comprising:

a clock data recovery (CDR) circuit coupled on an input side and an output side of the plurality of the ADCs, wherein the CDR circuit is configured to receive an ADC sample signal from the output of each ADC and in response thereto, to generate a channel timing signal and an ADC timing signal, the channel timing signal alternating between the first VGA-specific channel and the second VGA-specific channel, and the ADC timing signal including pulses that increment through each of the plurality of ADCs in the at least two ADC sets.

6. The network transceiver device of claim 5 , wherein the CDR circuit includes a phase detector configured to detect a phase of a signal received from each of the plurality of ADCs, wherein the phase detector of the CDR circuit is configured to determine a timing of an impulse response in the received signal from each ADC of the plurality of ADCs utilizing at least two precursor coefficients, a main coefficient, and at least two post cursor coefficients.

7. The network transceiver device of claim 1 ,

wherein the network transceiver device is configured to operate as a four-level pulse-amplitude modulated (PAM-4) transceiver.

8. The network transceiver device of claim 1 ,

wherein the first set of coefficient values and second set of coefficient values differ in value from each other.

9. The network transceiver device of claim 1 ,

wherein the first and second set of coefficient values are computed to minimize a squared error associated with an ADC sample of an analog input signal.

10. The network transceiver device of claim 1 ,

wherein the at least two sets of ADCs includes four sets of ADCs, with 16 ADCs included in each of the four sets.

11. A signal processing method, comprising:

amplifying received signals at a plurality of variable gain amplifiers (VGAs);

receiving amplified signals from the plurality of VGAs at each set of at least two sets of analog digital converters (ADCs), each set including a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs, wherein a first set of the at least two sets of ADCs is arranged in at least a first VGA-specific channel and a second set of the at least two sets of ADCs is arranged in at least a second VGA-specific channel;

receiving signals from the plurality of ADCs in each set of the at least two sets of ADCs at a plurality of feed-forward equalizers (FFEs) in either the first VGA-specific channel or the second VGA-specific channel; and

equalizing adaptively an output received from a corresponding ADC of the at least two sets of ADCs at each FFE, utilizing a plurality of equalization coefficients, the plurality of equalization coefficients including a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for the first VGA-specific channel and a second set of coefficient values for the second VGA-specific channel, the first and second set of coefficient values being computed independently of each other.

12. The method of claim 11 , further comprising:

receiving signals from the plurality of the FFEs at a plurality of decision feedback equalizers (DFEs); and

equalizing a respective output of a corresponding one of the plurality of FFEs in either the first VGA-specific channel or the second VGA-specific channel at each DFE.

13. The method of claim 11 , further comprising:

receiving a sample signal from the output of each ADC of the at least two sets of ADCs at a clock data recovery (CDR) circuit;

generating, via the CDR circuit, a channel timing signal and an ADC timing signal, the channel timing signal alternating between the first VGA-specific channel and the second VGA-specific channel, and the ADC timing signal including pulses that increment through each ADC of the plurality of ADCs in each set of the at least two sets of ADCs; and

driving the plurality of ADCs in each set of the at least two sets of ADCs using the channel timing signal and the ADC timing signal.

14. The method of claim 13 , wherein the CDR circuit includes a phase detector configured to detect a phase of a signal received from each ADC of the at least two sets of ADCs, wherein the phase detector of the CDR circuit is configured to determine a timing of an impulse response in the received sample signal from each ADC utilizing at least two precursor coefficients, a main coefficient, and at least two post cursor coefficients.

15. The method of claim 11 , wherein the signal processing method is performed in a four-level pulse-amplitude modulated (PAM-4) transceiver.

16. The method of claim 11 , wherein the first set of coefficient values and second set of coefficient values differ in value from each other.

17. The method of claim 11 , wherein the first and second set of coefficient values are computed to minimize a squared error associated with an ADC sample of analog input signal.