Semiconductor device and method
A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.
1. A semiconductor device comprising:
a first fin extending from a substrate;
a second fin extending from the substrate;
an epitaxial source/drain region in the first fin and the second fin, the epitaxial source/drain region having a lower surface and an upper surface, the upper surface being a first substantially planar surface;
an inter-layer dielectric (ILD) encapsulating the epitaxial source/drain region, the ILD having a first portion and a second portion, the first portion disposed over the epitaxial source/drain region, the second portion disposed under the epitaxial source/drain region, the second portion having a void region, the void region being different from the second portion, the void region exposing the lower surface of the epitaxial source/drain region; and
an isolation region disposed between the first fin and the second fin, the second portion of the ILD disposed between the isolation region and the epitaxial source/drain region.
2. The semiconductor device of claim 1 further comprising a source/drain contact extending through the first portion of the ILD, the source/drain contact contacting the upper surface of the epitaxial source/drain region.
3. The semiconductor device of claim 1 , wherein an entirety of the upper surface of the epitaxial source/drain region is covered by dielectric materials.
4. The semiconductor device of claim 1 , wherein the lower surface is a second substantially planar surface.
5. The semiconductor device of claim 1 , wherein the first substantially planar surface extends over the first fin and extends over the second fin.
6. The semiconductor device of claim 1 , wherein the void region is separated from the isolation region.
7. The semiconductor device of claim 6 , wherein the void region has a height, the void region is separated a distance from the isolation region, and a ratio between the height and the distance is between 0.5 and 2.
8. A semiconductor device comprising:
a first fin extending from a substrate;
a second fin extending from the substrate;
an epitaxial source/drain region in the first fin and the second fin, the epitaxial source/drain region having a lower surface and an upper surface, the upper surface having a first planar portion over the first fin and having a second planar portion over the second fin;
an inter-layer dielectric (ILD) encapsulating the epitaxial source/drain region, the ILD having a first portion and a second portion, the first portion disposed over the epitaxial source/drain region, the second portion disposed under the epitaxial source/drain region, the second portion having a void region, the void region being different from the second portion, the void region exposing the lower surface of the epitaxial source/drain region; and
an isolation region disposed between the first fin and the second fin, the second portion of the ILD disposed between the isolation region and the epitaxial source/drain region.
9. The semiconductor device of claim 8 further comprising:
a source/drain contact extending through the first portion of the ILD, the source/drain contact contacting the upper surface of the epitaxial source/drain region.
10. The semiconductor device of claim 8 , wherein an entirety of the upper surface of the epitaxial source/drain region is covered by dielectric materials.
11. The semiconductor device of claim 8 , wherein the upper surface of the epitaxial source/drain region is a substantially planar surface comprising the first planar portion and the second planar portion.
12. The semiconductor device of claim 8 , wherein the upper surface of the epitaxial source/drain region further has a faceted portion between the first planar portion and the second planar portion.
13. The semiconductor device of claim 8 , wherein the void region is separated from the isolation region.
14. The semiconductor device of claim 13 , wherein the void region has a height, the void region is separated a distance from the isolation region, and a ratio between the height and the distance is between 0.5 and 2.
15. A semiconductor device comprising:
an isolation region over a substrate;
a first fin extending from between neighboring portions of the isolation region;
a first epitaxial source/drain region in the first fin, the first epitaxial source/drain region having a bottom surface, a first planar upper surface over the first fin, and a first facet adjoining the first planar upper surface; and
an inter-layer dielectric (ILD) encapsulating the first epitaxial source/drain region, the ILD having a first portion and a second portion, the first portion disposed over the first epitaxial source/drain region, the second portion disposed between the first epitaxial source/drain region and the isolation region, the second portion having a void region, the void region adjoining the bottom surface of the first epitaxial source/drain region, the void region being separated from the isolation region by the ILD.
16. The semiconductor device of claim 15 further comprising:
a second fin extending from between neighboring portions of the isolation region, the first epitaxial source/drain region further disposed in the second fin, the first epitaxial source/drain region further having a second planar upper surface over the second fin, a second facet adjoining the second planar upper surface, and third facets adjoining the first planar upper surface and the second planar upper surface.
17. The semiconductor device of claim 15 further comprising:
a second fin extending from between neighboring portions of the isolation region, the first epitaxial source/drain region further disposed in the second fin, the first epitaxial source/drain region further having a second facet adjoining the first planar upper surface, the first planar upper surface extending continuously over the first fin and the second fin.
18. The semiconductor device of claim 15 further comprising:
a second fin extending from between neighboring portions of the isolation region;
a second epitaxial source/drain region in the second fin, the second epitaxial source/drain region having a second planar upper surface over the second fin and having a second facet adjoining the second planar upper surface; and
a gate structure on the first fin and the second fin, the gate structure adjacent the first epitaxial source/drain region and the second epitaxial source/drain region.
19. The semiconductor device of claim 18 , wherein the first epitaxial source/drain region adjoins the second epitaxial source/drain region, the void region disposed under contacting portions of the first epitaxial source/drain region and the second epitaxial source/drain region.
20. The semiconductor device of claim 18 further comprising:
a source/drain contact extending through the first portion of the ILD, the source/drain contact contacting the first planar upper surface of the first epitaxial source/drain region.