IP Library › Granted Patent US 11,676,881
Granted Patent B2
US 11,676,881 · App. 16/929,223 · Granted Jun 13, 2023

Semiconductor package, semiconductor assembly and method for fabricating a semiconductor package

Inventors: Ralf Otremba (Kaufbeuren, DE); Teck Sim Lee (Melaka, MY); Klaus Schiess (Allensbach, DE); Xaver Schloegel (Sachsenkam, DE); Lee Shuang Wang (Melaka, MY); Mohd Hasrul Zulkifli (Selangor, MY)
Assignee: Infineon Technologies AG
H01L23/3677H01L21/4871H01L23/12H01L23/3107
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,676,881
App. No.
16/929,223
Granted
Jun 13, 2023
Kind
B2
Abstract

A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.

Claims (23)

1. A semiconductor package, comprising: a chip carrier having a uniform thickness across the whole chip carrier and comprising a metal, a semiconductor chip attached to and electrically contacting the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package, which is located above the semiconductor chip, wherein a second side of the semiconductor package, which is located below the semiconductor chip and opposite the first side is configured to be surface mounted to an application board, wherein the chip carrier at the encapsulation body is exposed at the first side of the semiconductor package, wherein the first side of the semiconductor package is planar, and wherein an outer surface of the chip carrier is coplanar with an outer surface of the encapsulation body at the first side of the semiconductor package.

2. The semiconductor package of claim 1 , wherein the mounting hole completely extends through the semiconductor package from the first side to the second side.

3. The semiconductor package of claim 1 , wherein the semiconductor package comprises two mounting holes that are arranged at opposing edges of the semiconductor package.

4. The semiconductor package of claim 1 , wherein the mounting hole is arranged at the center of the first side of the semiconductor package.

5. The semiconductor package of claim 1 , wherein the mounting hole extends through the chip carrier.

6. The semiconductor package of claim el, wherein the chip carrier comprises a fixture portion configured to accommodate the mounting hole but no semiconductor chips.

7. The semiconductor package of claim 1 , wherein the mounting hole is arranged in the encapsulation body laterally besides the chip carrier.

8. The semiconductor package of claim 1 , wherein an inner surface of the mounting hole comprises an electrically insulating material to electrically insulate a screw in the mounting hole from the chip carrier.

9. The semiconductor package of claim 8 , wherein the electrically insulating material corresponds to the material of the encapsulation body.

10. The semiconductor package of claim 1 , further comprising:

external contacts for electrically contacting the semiconductor chip, wherein the external contacts are arranged on the second side of the semiconductor package.

11. A semiconductor assembly, comprising: a semiconductor package, comprising: a chip carrier having a uniform thickness across the whole chip carrier and comprising a metal, a semiconductor chip attached to and electrically contacting the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole, a heatsink arranged on a first side of the semiconductor package, the first side being located above the semiconductor chip, a screw arranged in the mounting hole and mounting the heatsink to the first side of the semiconductor package, and an application board, wherein a second side of the semiconductor package which is located below the semiconductor chip and opposite the first side is surface mounted to the application board, and wherein the chip carrier on the encapsulation body is exposed on the first side of the semiconductor package, wherein the first side of the semiconductor package is planar, and wherein an outer surface of the chip carrier is coplanar with an outer surface of the encapsulation body at the first side of the semiconductor package.

12. The semiconductor assembly of claim 11 , wherein the screw extends through the semiconductor package and through the application board.

13. The semiconductor assembly of claim 11 , wherein the mounting hole is arranged at the center of the first side of the semiconductor package.

14. The semiconductor assembly of claim 11 , wherein the mounting hole extends through the chip carrier.

15. The semiconductor assembly of claim 11 , wherein the chip carrier comprises a fixture portion configured to accommodate the mounting hole but no semiconductor chips.

16. A semiconductor package, comprising: a chip carrier having a uniform thickness across the whole chip carrier and comprising a metal, a semiconductor chip attached to and electrically contacting the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package, which is located above the semiconductor chip, wherein a second side of the semiconductor package, which is located below the semiconductor chip and opposite the first side is configured to be surface mounted to an application board, wherein the chip carrier at the encapsulation body is exposed at the first side of the semiconductor package, and wherein the mounting hole extends through the chip carrier.

17. The semiconductor package of claim 16 , wherein the first side of the semiconductor package is planar, and

wherein an outer surface of the chip carrier is coplanar with an outer surface of the encapsulation body on the first side of the semiconductor package.

18. The semiconductor package of claim 16 , wherein the mounting hole extends through a center of the chip carrier.

19. The semiconductor package of claim 16 , wherein the semiconductor package comprises two mounting holes that are arranged at opposing edges of the semiconductor package and extend through the chip carrier.

20. The semiconductor package of claim 16 , further comprising:

a plurality of semiconductor chips attached to the chip carrier.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2020
From: OTREMBA, RALF; LEE, TECK SIM; SCHIESS, KLAUS; SCHLOEGEL, XAVER; WANG, LEE SHUANG; ZULKIFLI, MOHD HASRUL
To: INFINEON TECHNOLOGIES AG
Reel/Frame 054675/0386 →
Priority Claims (1)
DE 10 2019 119 118.1 · Jul 15, 2019 · national
Continuity (1)
Related Publication 20210020539A1 · Jan 21, 2021
Cited By (1)
US 12,557,652