IP Library › Granted Patent US 11,678,441
Granted Patent B2
US 11,678,441 · App. 16/950,910 · Granted Jun 13, 2023

Manufacturing method of circuit carrier board structure

Inventors: Wei-Ti Lin (Hsinchu County, TW); Chun-Hsien Chien (Hsinchu, TW); Chien-Chou Chen (Hsinchu County, TW); Fu-Yang Chen (Hsinchu County, TW); Ra-Min Tain (Hsinchu County, TW)
Assignee: Unimicron Technology Corp.
H05K3/4644H05K1/111H05K1/115H05K1/181H05K3/007H05K3/0097H05K3/28H05K3/303H05K3/4007H05K3/421H05K3/429H05K2201/09136H05K2201/09509H05K2201/09827H05K2201/10234H05K2201/10522
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Quick Facts
Patent No.
US 11,678,441
App. No.
16/950,910
Granted
Jun 13, 2023
Kind
B2
Abstract

A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

Claims (39)

1. A manufacturing method of a circuit carrier board structure, comprising:

providing a temporary carrier board;

forming a first substrate on the temporary carrier board, wherein the first substrate has a first surface and a second surface opposite to the first surface, and the step of forming the first substrate comprises:

forming a release layer on the temporary carrier board; and

forming a plurality of first build-up layers stacked on the release layer in sequence,

wherein each of the first build-up layers comprises a first dielectric layer and a first circuit layer,

wherein the first build-up layers are electrically connected to one another;

forming a plurality of connection pads on the first surface, wherein the connection pads are electrically connected to the first circuit layer, and a linewidth of the first circuit layer is smaller than a linewidth of each of the connection pads;

providing a second substrate having a third surface and a fourth surface opposite to the third surface;

forming a solder resist layer covering the first surface and the fourth surface, wherein the solder resist layer exposes a portion of the connection pads, the first circuit layer, and a second circuit layer of the second substrate; and

performing a surface treatment procedure;

disposing an adhesive layer on one of the first substrate and the second substrate, wherein the adhesive layer is located between the first substrate and the second substrate;

combining the second surface of the first substrate to the third surface of the second substrate; and

removing the temporary carrier board,

wherein the first substrate is electrically connected to the second substrate.

2. The manufacturing method of the circuit carrier board structure of claim 1 , wherein the step of providing the second substrate comprises:

providing a second base;

forming a plurality of second build-up layers sequentially stacked on the second base, wherein each of the second build-up layers comprises a second dielectric layer and the second circuit layer; and

forming a plurality of conductive pads on the third surface, wherein the conductive pads are electrically connected to the second circuit layer,

wherein the second build-up layers are electrically connected to one another.

3. The manufacturing method of the circuit carrier board structure of claim 2 , further comprising:

forming a plurality of through-holes passing through the first substrate and exposing the conductive pads;

forming a seed layer on the first surface, wherein the seed layer is filled in the through-holes and in contact with the conductive pads;

forming a photoresist pattern covering a portion of the seed layer to expose a portion of the seed layer;

forming a plurality of conductive structures from the exposed portion of the seed layer, wherein each of the conductive structures is electrically connected to each of the conductive pads and the first circuit layer; and

removing the photoresist pattern and the seed layer covered by the photoresist pattern.

4. The manufacturing method of the circuit carrier board structure of claim 1 , wherein the step of forming the first substrate further comprises:

forming a plurality of conductive pillars on the second surface, wherein the conductive pillars are electrically connected to the first circuit layer.

5. The manufacturing method of the circuit carrier board structure of claim 4 , wherein the step of providing the second substrate comprises:

providing a second base;

forming a plurality of second build-up layers sequentially stacked on the second base, wherein each of the second build-up layers comprises a second dielectric layer and the second circuit layer; and

forming a plurality of conductive blind vias on the third surface, wherein the conductive blind vias are electrically connected to the second circuit layer,

wherein the second build-up layers are electrically connected to one another.

6. The manufacturing method of the circuit carrier board structure of claim 5 , wherein the step of combining the first substrate to the second substrate further comprises:

combining the conductive pillars to the conductive blind vias, such that the conductive pillars are electrically connected and filled in the conductive blind vias to form a plurality of conductive structures,

wherein the conductive structures are electrically connected to the second circuit layer and the first circuit layer.

7. The manufacturing method of the circuit carrier board structure of claim 1 , further comprising:

disposing a plurality of electronic elements on the first surface of the first substrate, wherein the electronic elements are electrically connected to the connection pads and the first circuit layer; and

disposing a plurality of solder balls on the solder resist layer, and the solder balls electrically connected to the second circuit layer.

Priority Claims (1)
TW 107136704 · Oct 18, 2018 · national
Continuity (3)
Division 16244113 · Jan 10, 2019
Provisional Application 62682181 · Jun 8, 2018
Related Publication 20210076508A1 · Mar 11, 2021