Semiconductor device and method of forming the same
A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.
1. A device, comprising:
an interconnect structure;
a barrier multi-layer structure over the interconnect structure, the barrier multi-layer structure comprising a first metal nitride layer and a second metal nitride layer over the first metal nitride layer;
an oxide layer over the barrier multi-layer structure, wherein the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure, and an oxygen concentration of the oxide layer decreases downwardly;
a pad metal layer over the oxide layer; and
a passivation layer in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.
2. The device of claim 1 , wherein the oxide layer is thinner than the first metal nitride layer and the second metal nitride layer.
3. The device of claim 1 , wherein the barrier multi-layer structure further comprises a metal layer below the first metal nitride layer and in contact with the interconnect structure.
4. The device of claim 3 , wherein the metal layer is thinner than the first metal nitride layer, and the first metal nitride layer is thinner than the second metal nitride layer.
5. The device of claim 3 , wherein the metal layer is made of tantalum, and the first metal nitride layer and the second metal nitride layer are made of tantalum nitride.
6. The device of claim 3 , wherein the passivation layer is in contact with the metal layer of the barrier multi-layer structure.
7. The device of claim 1 , further comprises a transistor electrically connected to the interconnect structure.
8. A device, comprising:
an interconnect structure having a metal structure;
a first passivation layer over the interconnect structure;
a barrier layer over the first passivation layer and having a portion in contact with the metal structure of the interconnect structure;
an oxide layer over the barrier layer, wherein the oxide layer is an oxide of the barrier layer, and the oxide layer is porous;
a pad metal layer over the oxide layer; and
a second passivation layer in contact with the barrier layer, the oxide layer, and the pad metal layer, wherein the second passivation layer comprises a first layer and a second layer, the first layer is made of undoped silicate glass (USG) and the second layer is made of silicon nitride (SiN).
9. The device of claim 8 , wherein the barrier layer comprises a tantalum-based material, and the oxide layer comprises tantalum oxide.
10. The device of claim 8 , wherein the barrier layer comprises a metal layer, a first metal nitride layer over the metal layer, and a second metal nitride layer over the first metal nitride layer.
11. The device of claim 10 , wherein the metal layer is thinner than the first metal nitride layer and the first metal nitride layer is thinner than the second metal nitride layer.
12. The device of claim 8 , wherein a bottommost surface of the second passivation layer is lower than a topmost surface of the first passivation layer.
13. The device of claim 8 , wherein a thickness of the oxide layer is in a range from about 1 angstrom (Å) to about 500 Å.
14. The device of claim 8 , further comprises a transistor electrically connected to the interconnect structure.
15. A device, comprising:
an interconnect structure;
a barrier layer stack over the interconnect structure, the barrier layer stack comprising:
a metal layer having a first thickness;
a first metal nitride layer over the metal layer and having a second thickness; and
a second metal nitride layer over the first metal nitride layer and having a third thickness;
an oxide layer over the barrier layer stack and having a fourth thickness, wherein the fourth thickness is a smallest one among the first, second, third, and fourth thicknesses, and wherein the oxide layer is an oxide of the second metal nitride layer;
a pad metal layer over the oxide layer; and
a passivation layer in contact with the barrier layer stack, the oxide layer, and the pad metal layer.
16. The device of claim 15 , wherein the first metal nitride layer and the second metal nitride layer are made of a same material.
17. The device of claim 15 , wherein the oxide layer and the second metal nitride layer comprises a same metal element.
18. The device of claim 15 , wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness.
19. The device of claim 15 , wherein the barrier layer stack is free of oxide.
20. The device of claim 15 , further comprises a transistor electrically connected to the interconnect structure.