IP Library › Granted Patent US 11,683,930
Granted Patent B2
US 11,683,930 · App. 17/403,158 · Granted Jun 20, 2023

Method of fabricating semiconductor device

Inventors: Da-Zen Chuang (Taipei, TW); Pin-Hsiu Hsieh (Taoyuan, TW); Chih-Chung Sun (Zhubei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H10B12/50G11C11/161H01F10/329H01F10/3254H01L21/28035H01L23/528H01L23/5226H01L23/585H01L29/401H01L29/4916H10B12/053H10B12/315H10B12/34H10B12/482H10B61/22H10N50/01H10N50/80
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Quick Facts
Patent No.
US 11,683,930
App. No.
17/403,158
Granted
Jun 20, 2023
Kind
B2
Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.

Claims (11)

1. A semiconductor device, comprising:

a semiconductor substrate comprising a memory region and a logic region away from the memory region;

a memory cell disposed in the memory region;

a processing unit disposed in the logic region, wherein the processing unit includes a control unit and a processing peripheral circuit communicating between the control unit of the processing unit and the memory cell;

a plurality of first logic transistors disposed in the memory region and surrounding the memory cell;

a plurality of second logic transistors disposed in the control unit of the processing unit deposited in the logic region; and

a plurality of third logic transistors disposed in the processing peripheral circuit of the processing unit deposited in the logic region and surrounding the second logic transistors.

2. The semiconductor device of claim 1 , further comprising:

a guard ring disposed on the semiconductor substrate and surrounding the memory cell, the first logic transistors, the second logic transistors, and the third logic transistors.

3. The semiconductor device of claim 1 , further comprising:

a guard ring disposed on the semiconductor substrate, wherein the memory cell is disposed between the second logic transistor and the guard ring.

Continuity (2)
Division 16584006 · Sep 26, 2019
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