Reducing programming disturbance in memory devices
Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block.
1. An apparatus, comprising:
a memory structure comprising,
multiple blocks of memory cell strings, respectively comprising multiple sub-blocks of memory cell strings, wherein the memory cell strings respectively comprise multiple memory cells extending between a source select gate and a drain select gate, and wherein the memory cell strings further comprise a respective common channel material; and
a memory device controller, comprising control circuitry configured to perform operations on the memory structure, comprising,
during a first interval of a programming operation, precharging channel material of memory cell strings in multiple sub-blocks within a block to a precharge voltage, the multiple sub-blocks including a selected sub-block containing a selected memory cell, and at least one unselected sub-block that does not contain a selected memory cell; and
during a second interval of the programming operation, after the first interval, applying a programming voltage to a first access line coupled to the selected memory cell in the selected sub-block, wherein an unselected memory cell in the unselected sub-block is also coupled to the first access line;
wherein during the second interval of the programing operation, the channel material in the unselected sub-block is charged to a first voltage higher than the precharge voltage in response to a coupled voltage induced on the channel material in the unselected sub-block as a result of the programming voltage on the first selected access line.
2. The apparatus of claim 1 , wherein the multiple memory cell strings with a block collectively form multiple vertically offset levels of memory cells, wherein each level of memory cells in multiple sub-blocks are coupled to a respective common access line.
3. The apparatus of claim 2 , wherein all memory cells at a respective level within a block of memory cell strings are coupled to a common access line.
4. The apparatus of claim 1 , wherein the precharging further comprises enabling a select gate of a string of memory cells in the unselected sub-block to couple the precharge voltage to the channel material of the string of memory cells in the unselected sub-block.
5. The apparatus of claim 4 , wherein the enabled select gate in the unselected sub-block during precharging is the drain select gate.
6. The apparatus of claim 4 , wherein the enabled select gate in the unselected sub-block during precharging is the source select gate.
7. The apparatus of claim 1 , further comprising allowing the channel material of the string of memory cells in the unselected sub-block to float during the second interval of the programming operation.
8. The apparatus of claim 7 , wherein allowing the channel material of the string of memory cells in the unselected sub-block to float comprises grounding a select line coupled to a select gate of the string of memory cells in the unselected sub-block.
9. The apparatus of claim 1 , further comprising applying a program enable voltage to a data line during the programming operation, wherein the data line is coupled to strings of memory cells in the unselected sub-block and in the selected sub-block.
10. The apparatus of claim 9 , wherein applying a program enable voltage to the data line comprises coupling the data line to a ground of a memory device including the block of memory cells.
11. The apparatus of claim 10 , further comprising enabling a select gate in a string of memory cells to couple the program enable voltage to channel material of the selected memory cell during the programming operation.
12. A memory structure, comprising:
a block of vertically-extending memory cell strings, the block including multiple sub-blocks, each memory cell string including a pillar of semiconductor channel material, and extending between a source and a data line, wherein each memory cell in a vertical string is coupled to a respective access line, and wherein access lines connect to memory cells in multiple sub-blocks;
a memory device controller, comprising control circuitry configured to perform operations on the memory structure, comprising:
during an initial part of a programming operation, precharging the pillars of multiple memory cell strings in multiple sub-blocks in the block by applying a precharge voltage to the pillars of the memory cell strings; and
during a subsequent part of the programming operation, applying a programming voltage to a selected access line coupled to a selected memory cell in the selected sub-block; and
wherein during the subsequent part of the programing operation, the pillar of at least one unselected memory cell string in an unselected sub-block is charged to a first voltage higher than the precharge voltage in response to a coupled voltage induced on the channel material by the programming voltage on the selected access line.
13. The memory structure of claim 12 , wherein the selected access line is further coupled to the unselected memory cell in the unselected sub-block.
14. The memory structure of claim 12 , wherein the channel material of the strings of memory cells in both the selected sub-block and the unselected sub-block is precharged to the precharge voltage during the initial part of the programming operation.
15. The memory structure of claim 14 , wherein the operations further comprise allowing the pillar of the memory cells strings in the unselected sub-block to float during the subsequent part of the programming operation.
16. The memory structure of claim 15 , wherein the allowing the pillars of the memory cells strings in the unselected sub-block during a subsequent part of the programming operation comprises placing respective drain select gates of memory cells strings of the unselected sub-block in a non-conducting state.
17. The memory structure of claim 16 , wherein the operations comprise, during the subsequent part of the programing operation, placing the drain select gate of the selected memory cell string in a conducting state.
18. A memory device, comprising:
a memory array comprising,
a block of memory cell strings, comprising,
multiple strings of NAND memory cells arranged in multiple sub-blocks, the multiple strings of NAND memory cells extending between a source and an associated data line of multiple data lines, each string including,
multiple NAND memory cells arranged at vertically offset levels along a semiconductor pillar;
a source select gate between the multiple NAND memory cells and the source;
a drain select gate between the NAND memory cells and the associated data line; and
multiple access lines coupled to memory cells in a respective level in at least first and second sub-blocks of the multiple sub-blocks;
a memory device controller, comprising control circuitry configured to perform operations comprising,
performing a programming operation on a selected memory cell in a selected string of a selected sub-block of the first and second sub-blocks, the programming operation comprising a first portion and a second portion,
wherein the first portion of the programming operation comprises pre-charging the semiconductor pillars of multiple strings of memory cells in both the selected sub-block and an unselected sub-block with a precharge voltage, including placing the drain select gates of the memory cells strings in a conducting state, and applying a precharge voltage to the data lines in both the selected sub-block and the unselected sub-block;
wherein the second portion of the programming operation comprises,
after precharging the semiconductor pillars of the strings of memory cells in the selected sub-block and the unselected sub-block, placing the drain select gates in the unselected sub-block in a non-conducting state;
maintaining an elevated voltage on data lines not coupled to the selected string containing the selected memory cell; and
applying a programming voltage to a first access line coupled to the selected memory cell in the selected sub-block of the block of memory cells and to at least one unselected memory cell in the unselected sub-block; and
while applying the programming voltage to the first access line, placing the drain select gate of the selected string in a conductive state.
19. The memory device of claim 18 , wherein the first portion of the programming operation further comprises applying a third voltage to the selected access line and to multiple unselected access lines to establish a conducting condition in channels of the memory cells coupled to the access lines.