Seal material for air gaps in semiconductor devices
The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.
1. A semiconductor device, comprising:
a gate electrode on a fin region;
a source/drain (S/D) structure on the fin region;
an etch stop layer on a sidewall of the S/D structure;
a seal layer between the gate electrode and the etch stop layer, wherein the seal layer comprises a silicon carbide material doped with oxygen; and
an air gap in physical contact with the etch stop layer and surrounded by the seal layer, the fin region, the gate electrode, and the S/D structure.
2. The semiconductor device of claim 1 , further comprising:
a gate dielectric layer on a sidewall of the gate electrode; and
a spacer comprising a first portion on a sidewall of the gate dielectric layer and a second portion on a top surface of the fin region.
3. The semiconductor device of claim 2 , wherein the air gap is in physical contact with the etch stop layer and the first and second portions of the spacer.
4. The semiconductor device of claim 1 , wherein top surfaces of the seal layer and the etch stop layer are substantially coplanar.
5. The semiconductor device of claim 1 , wherein a density of the seal layer is between about 2.0 g/cm 3 and about 3.2 g/cm 3 .
6. The semiconductor device of claim 1 , wherein an oxygen atomic content of the seal layer is between about 30% and about 55%.
7. The semiconductor device of claim 1 , wherein a carbon atomic content of the seal layer is between about 10% and about 35%.
8. The semiconductor device of claim 1 , wherein a silicon atomic content of the seal layer is between about 25% and about 35%.
9. The semiconductor device of claim 1 , further comprising a self-aligned contact (SAC) on the S/D structure, wherein the SAC comprises the silicon carbide material doped with oxygen and has a top surface substantially coplanar with a top surface of the seal layer.
10. A semiconductor device, comprising:
a gate structure on a fin region, comprising;
a gate electrode; and
a first self-aligned contact (SAC) formed on the gate electrode;
a source/drain (S/D) contact;
a second SAC formed on the S/D contact;
a seal layer comprising a silicon carbide material doped with oxygen, wherein the seal layer further comprises:
a first portion between the gate structure and the S/D contact; and
a second portion on top surfaces of the first SAC and the second SAC; and
an air gap surrounded by the seal layer, the fin region, the gate electrode, and the S/D contact.
11. The semiconductor device of claim 10 , wherein a density of the seal layer is between about 2.0 g/cm 3 and about 3.2 g/cm 3 .
12. The semiconductor device of claim 10 , wherein an oxygen atomic content of the seal layer is between about 30% and about 55%.
13. The semiconductor device of claim 10 , further comprising a via extending through the second portion of the seal layer and in physical contact with the second SAC.
14. The semiconductor device of claim 10 , further comprising a gate dielectric layer and a spacer, wherein the spacer comprises a first portion on a sidewall of the gate dielectric layer and a second portion on a top surface of the fin region.
15. The semiconductor device of claim 10 , wherein the first SAC comprises silicon nitride and the second SAC comprises the silicon carbide material doped with oxygen.
16. A method for forming a semiconductor device, comprising:
forming an opening between a gate structure and a source/drain (S/D) structure of the semiconductor device, wherein the gate structure comprises a gate dielectric layer; and
forming a seal layer on the opening between the gate structure and the S/D structure, comprising:
depositing a silicon carbide material in the opening to form a first portion of the seal layer, wherein the first portion of the seal layer entraps a pocket of air in the opening between the gate dielectric layer and the S/D structure;
depositing the silicon carbide material on top surfaces of the gate structure and the S/D structure to form a second portion of the seal layer; and
performing an oxygen anneal process on the seal layer.
17. The method of claim 16 , wherein the first portion of the seal layer is deposited towards a top of the opening.
18. The method of claim 16 , wherein depositing the first and second portions of the seal layer comprises flowing tetramethyldisiloxane (TSMDSO), hydrogen gas, and oxygen gas into a deposition chamber.
19. The method of claim 18 , wherein a flow ratio of the hydrogen gas to the oxygen gas is between about 20 and about 30.
20. The method of claim 16 , further comprising removing the second portion of the seal layer with a planarization process.