Method of forming first and second contacts self-aligned top source/drain region of a vertical field-effect transistor

1. A method of forming a semiconductor structure, comprising:

forming at least one fin disposed over a top surface of a substrate, the at least one fin providing a vertical transport channel for a vertical transport field-effect transistor;

forming a top source/drain region disposed over a top surface of the at least one fin;

forming an interlevel dielectric layer surrounding the top source/drain region and the at least one fin;

forming a first contact trench in the interlevel dielectric layer at a first end of the at least one fin for a bottom source/drain contact of the vertical transport field-effect transistor and a second contact trench in the interlevel dielectric layer at a second end of the at least one fin for a gate contact of the vertical transport field-effect transistor, the first and second contact trenches being self-aligned to the top source/drain region, the first contact trench abutting a portion of the top source/drain region at the first end of the at least one fin and the second contact trench abutting a portion of the top source/drain region at the second end of the at least one fin;

forming inner spacers on sidewalls of the first contact trench and the second contact trench; and

forming contact material in the first contact trench and the second contact trench between the inner spacers;

wherein the contact material comprises a stressor material that induces vertical strain in the at least one fin.

2. The method of claim 1 , wherein:

the first contact trench provides an opening that reveals a portion of a top surface of a bottom source/drain region at the first end of the at least one fin; and

the second contact trench provides an opening that reveals a portion of a gate conductor of a gate stack surrounding the at least one fin at the second end of the at least one fin.

3. The method of claim 1 , wherein forming the contact material comprises selecting a designated set of pressure deposition conditions for forming the stressor material to induce a desired type of vertical strain in the at least one fin.

4. The method of claim 1 , wherein the vertical transport field-effect transistor (VTFET) comprises a p-type VTFET, and wherein forming the contact material comprises depositing the stressor material with a first polarity inducing compressive vertical strain in the at least one fin.

5. The method of claim 1 , wherein the vertical transport field-effect transistor (VTFET) comprises an n-type VTFET, and wherein forming the contact material comprises depositing the stressor material with a second polarity inducing a tensile vertical strain in the at least one fin.

6. The method of claim 1 , further comprising:

forming a hard mask disposed over the at least one fin;

forming shallow trench isolation regions disposed in the top surface of the substrate at the first and second ends of the at least one fin;

forming a bottom source/drain region in the top surface of the substrate between the shallow trench isolation regions;

forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding a portion of sidewalls of the at least one fin;

forming a gate dielectric layer disposed over a top surface of the bottom spacer, surrounding exposed sidewalls of the at least one fin, and disposed over the hard mask; and

forming a gate conductor layer disposed over the gate dielectric layer.

7. The method of claim 6 , further comprising:

forming a liner layer disposed over the gate conductor layer;

forming a first portion of the interlevel dielectric layer over the liner layer; and

planarizing the first portion of the interlevel dielectric layer to expose a top surface of the liner layer disposed over the at least one fin.

8. The method of claim 7 , further comprising:

removing a portion of the liner layer exposed by the first portion of the interlevel dielectric layer;

removing portions of the gate conductor layer and the gate dielectric layer to reveal a top surface of the hard mask; and

removing the hard mask to expose the top surface of the at least one fin.

9. The method of claim 8 , further comprising:

performing an isotropic etch that removes portions of the liner layer, the gate conductor layer and the gate dielectric layer to create divots between the at least one fin and a remaining portion of the liner layer; and

forming a top spacer in the divots between the at least one fin and the remaining portion of the liner layer.

10. The method of claim 9 , further comprising:

forming the top source/drain region over the top surface of the at least one fin;

forming a second portion of the interlevel dielectric layer over the top source/drain region; and

planarizing the second portion of the interlevel dielectric layer.

11. The method of claim 10 , further comprising:

forming the first contact trench by patterning a first opening in the first and second portions of the interlevel dielectric layer utilizing directional reactive-ion etching to reveal a portion of the top surface of the bottom source/drain region at the first end of the at least one fin;

forming the second contact trench by patterning a second opening in the first and second portions of the interlevel dielectric layer utilizing directional reactive-ion etching to reveal a portion of the gate conductor layer at the second end of the at least one fin; and

forming the inner spacers on sidewalls of the first contact trench and the second contact trench.

12. The method of claim 11 , further comprising:

forming a third contact trench by patterning a third opening in the first and second portions of the interlevel dielectric layer utilizing directional reactive-ion etching to reveal a portion of the top surface of the top source/drain region; and

forming the contact material by depositing the stressor material in the first, second and third contact trenches.

13. The method of claim 12 , further comprising:

removing the first and second portions of the interlevel dielectric layer; and

forming an additional interlevel dielectric layer to increase stress transfer from the stressor material to the at least one fin.

14. The method of claim 3 wherein forming the contact material comprises utilizing a magnetron sputtering process with an intrinsic compressive stress.

15. The method of claim 3 wherein the contact material comprises tungsten, and wherein forming the contact material comprises depositing tungsten utilizing a magnetron sputtering process with a value for a pressure of argon selected to produce one of a compressive strain and a tensile strain in the at least one fin in a vertical fin direction.

16. The method of claim 15 wherein the value of the pressure of argon is selected to be less than 0.5 Pascals (Pa) to produce tensile strain in the at least one fin in the vertical fin direction.

17. The method of claim 15 wherein the value of the pressure of argon is selected to be approximately 2.0 Pascals (Pa) to produce compressive strain in the at least one fin in the vertical fin direction.

18. The method of claim 3 wherein the contact material comprises tungsten nitride, and wherein forming the contact material comprises tuning a concentration of nitrogen during deposition of the tungsten nitride to induce the desired type of vertical strain in the at least one fin.

19. The method of claim 3 wherein selecting the designated set of pressure deposition conditions for forming the stressor material to induce the desired type of vertical strain in the at least one fin comprises:

selecting a pressure of argon to be utilized in a magnetron sputtering process for forming the contact material; and

selecting a concentration of nitrogen utilized in the magnetron sputtering process for forming the contact material.