Efficient memory activation at runtime
The present disclosure is directed to efficient memory activation at runtime. A memory module (e.g., a memory riser) being added to a device would typically cause the device to enter system management mode (SMM) to activate the memory module. However, activation (e.g., memory module initialization, hardware training and system reconfiguration) in SMM may substantially delay the resumption of normal operations. Consistent with the present disclosure, at least the memory module initialization and hardware training portions of the activation may be performed by an operating system (OS) in the device, allowing normal device operation to continue during the activation. The OS portion of the activation may generate configuration data. In at least one embodiment, the configuration data may be applied for use in SMM. For example, a system management interrupt (SMI) handler may apply the configuration data during a quiescent period (e.g., a period of inactivity) that occurs during SMM.
1. A device comprising:
interface circuitry;
programmable circuitry; and
instructions to cause the programmable circuitry to:
configure memory controller circuitry, during training, to interact with memory;
configure the interface circuitry, during the training, to interact with the memory;
determine a new memory configuration; and
after the training, when memory transactions are not in-process, re-configure the memory controller circuitry and the interface circuitry based on the new memory configuration.
2. The device of claim 1 , wherein the programmable circuitry is to re-configure the memory controller circuitry and the interface circuitry based on the new memory configuration after entering a system management mode.
3. The device of claim 2 , wherein the programmable circuitry is to activate a system management interrupt to enter the system management mode.
4. The device of claim 1 , wherein the programmable circuitry is to configure the memory controller circuitry, during the training, to interact with the memory based on at least one of an amount of the memory, a type of the memory, or a speed of the memory.
5. The device of claim 1 , wherein the interface circuitry is dual data rate interface circuitry.
6. The device of claim 1 , wherein the programmable circuitry is to configure the interface circuitry, during the training, with timing parameters corresponding to the memory.
7. The device of claim 1 , wherein the memory is a first memory integrated circuit (IC) in circuit with a second memory IC, the interface circuitry in circuit with the first memory IC and the second memory IC.
8. The device of claim 7 , wherein the first memory IC, the second memory IC, and the interface circuitry are located in a same memory circuit.
9. At least one machine-readable storage device comprising instructions to cause programmable circuitry to at least:
train memory controller circuitry to interact with memory;
train interface circuitry to interact with the memory;
determine a new memory configuration; and
after the programmable circuitry trains the memory controller circuitry and the interface circuitry, configure the memory controller circuitry and the interface circuitry based on the new memory configuration when memory transactions are not in-process,.
10. The at least one machine-readable storage device of claim 9 , wherein the instructions are to cause the programmable circuitry to configure the memory controller circuitry and the interface circuitry based on the new memory configuration data after entering a system management mode.
11. The at least one machine-readable storage device of claim 10 , wherein the instructions are to cause the programmable circuitry to activate a system management interrupt to enter the system management mode.
12. The at least one machine-readable storage device of claim 9 , wherein the instructions are to cause the programmable circuitry to train the memory controller circuitry to interact with the memory based on at least one of an amount of the memory, a type of the memory, or a speed of the memory.
13. The at least one machine-readable storage device of claim 9 , wherein the interface circuitry is dual data rate interface circuitry.
14. The at least one machine-readable storage device of claim 9 , wherein the instructions are to cause the programmable circuitry to train the interface circuitry by configuring the interface circuitry with timing parameters corresponding to the memory.
15. The at least one machine-readable storage device of claim 9 , wherein the memory is a first memory integrated circuit (IC) in circuit with a second memory IC, the instructions to cause the programmable circuitry to configure the interface circuitry to interact with the first memory IC and the second memory IC.
16. The at least one machine-readable storage device of claim 15 , wherein the first memory IC, the second memory IC, and the interface circuitry are located in a same memory circuit.
17. A method comprising:
configuring, by executing an instruction with programmable circuitry, memory controller circuitry to interact with memory, during a training phase;
configuring, by executing an instruction with the programmable circuitry, interface circuitry to interact with the memory, during the training phase;
determining, by executing an instruction with the programmable circuitry, a new memory configuration; and
after the training phase, re-configuring, by executing an instruction with the programmable circuitry, the memory controller circuitry and the interface circuitry based on the new memory configuration, when memory transactions are not in-process.
18. The method of claim 17 , wherein the re-configuring of the memory controller circuitry and the interface circuitry based on the new memory configuration is performed after entering a system management mode.
19. The method of claim 18 , further including activating a system management interrupt to enter the system management mode.
20. The method of claim 17 , wherein the configuring of the memory controller circuitry to interact with the memory, during the training phase, is based on at least one of an amount of the memory, a type of the memory, or a speed of the memory.
21. The method of claim 17 , wherein the interface circuitry is dual data rate interface circuitry.
22. The method of claim 17 , wherein the configuring of the interface circuitry to interact with the memory, during the training phase, includes configuring the interface circuitry with timing parameters corresponding to the memory.
23. The method of claim 17 , wherein the memory is a first memory integrated circuit (IC) in circuit with a second memory IC, and further including configuring the interface circuitry to interact with the second memory IC.
24. The method of claim 23 , wherein the first memory IC, the second memory IC, and the interface circuitry are located in a same memory circuit.