Peak and average ICC reduction by tier-based sensing during program verify operations of non-volatile memory structures
A method for programming a memory block of a non-volatile memory structure, wherein the method provides, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.
1. A method for programming a memory block of a non-volatile memory structure, comprising:
during a program verify operation:
selecting only a partial segment of memory cells of a memory block for bit scan mode;
applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells; and
initiating a bit scan mode of the selected memory cells.
2. The method according to claim 1 , wherein the program verify operation is a stage of a SLC-type programming sequence.
3. The method according to claim 1 , wherein the memory block is comprised of three-dimensional NAND-type memory cells.
4. The method according to claim 1 , wherein the sensing bias voltage is simultaneously applied to all of the one or more bit lines.
5. The method according to claim 1 , wherein the partial segment of memory cells is comprised of one out of every sixteen memory cells.
6. The method according to claim 1 , wherein the partial segment of memory cells is comprised of two out of every sixteen memory cells.
7. The method according to claim 1 , wherein the partial segment of memory cells is comprised of four out of every sixteen memory cells.
8. A memory controller, comprising:
a first port configured to couple to a non-volatile memory structure, the structure comprising a memory block; and
the memory controller configured to:
during a program verify operation:
select only a partial segment of memory cells of the memory block for bit scan mode;
apply a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells; and
initiate a bit scan mode of the selected memory cells.
9. The memory controller according to claim 8 , wherein the program verify operation is a stage of a SLC-type programming sequence.
10. The memory controller according to claim 8 , wherein the memory block is comprised of three-dimensional NAND-type memory cells.
11. The memory controller according to claim 8 , wherein the sensing bias voltage is simultaneously applied to all of the one or more bit lines.
12. The memory controller according to claim 8 , wherein the partial segment of memory cells is comprised of one out of every sixteen memory cells.
13. The memory controller according to claim 8 , wherein the partial segment of memory cells is comprised of two out of every sixteen memory cells.
14. The memory controller according to claim 8 , wherein the partial segment of memory cells is comprised of four out of every sixteen memory cells.
15. A non-volatile memory system, comprising:
a memory structure;
a memory controller coupled to the memory structure and:
during a program verify operation of a memory block of the memory structure:
selecting only a partial segment of memory cells of a memory block for bit scan mode;
applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells; and
initiating a bit scan mode of the selected memory cells.
16. The non-volatile memory system according to claim 15 , wherein the program verify operation is a stage of a SLC-type programming sequence.
17. The non-volatile memory system according to claim 15 , wherein the sensing bias voltage is simultaneously applied to all of the one or more bit lines.
18. The non-volatile memory system according to claim 15 , wherein the partial segment of memory cells is comprised of one out of every sixteen memory cells.
19. The non-volatile memory system according to claim 15 , wherein the partial segment of memory cells is comprised of two out of every sixteen memory cells.
20. The non-volatile memory system according to claim 15 , wherein the partial segment of memory cells is comprised of four out of every sixteen memory cells.