Semiconductor package including heat dissipation layer
A semiconductor package includes an interposer including first and second surfaces opposite to each other. The semiconductor package also includes a heat dissipation layer disposed on the first surface of the interposer and a first semiconductor die mounted on the first surface of the interposer. The semiconductor package additionally includes a stack of second semiconductor dies mounted on the second surface of the interposer. The semiconductor package further includes a thermally conductive connection part for transferring heat from the stack of the second semiconductor dies to the heat dissipation layer.
1. A semiconductor package comprising:
an interposer including first and second surfaces opposite to each other;
a heat dissipation layer disposed on the first surface of the interposer;
a first semiconductor die mounted on the first surface of the interposer;
a stack of second semiconductor dies mounted on the second surface of the interposer; and
a thermally conductive connection part for transferring heat from the stack of the second semiconductor dies to the heat dissipation layer,
wherein the interposer further includes a passivation layer exposing a surface of the heat dissipation layer on the first surface of the interposer.
2. The semiconductor package of claim 1 , wherein the heat dissipation layer is positioned to overlap the stack of the second semiconductor dies.
3. The semiconductor package of claim 1 , wherein the first semiconductor die is positioned to not overlap the heat dissipation layer.
4. The semiconductor package of claim 1 , wherein the first semiconductor die is positioned to not overlap the stack of the second semiconductor dies.
5. The semiconductor package of claim 1 , wherein the thermally conductive connection part includes:
a plurality of thermally conductive vias connected to the heat dissipation layer while substantially vertically penetrating the interposer; and
a plurality of thermally conductive connectors positioned between the second surface of the interposer and the stack of the second semiconductor dies and thermally connected to the thermally conductive vias.
6. The semiconductor package of claim 5 ,
wherein the stack of the second semiconductor dies includes an insulation layer electrically insulating the thermally conductive connectors from the second semiconductor dies, and
wherein the thermally conductive connectors are connected to a surface of the insulation layer.
7. The semiconductor package of claim 5 , wherein the thermally conductive connection part includes a plurality of thermally conductive pads disposed on the second surface of the interposer, wherein the plurality of thermally conductive pads thermally connect the thermally conductive connectors to the thermally conductive vias.
8. The semiconductor package of claim 7 , further comprising an electrical connection part electrically connecting the stack of the second semiconductor dies to the first semiconductor die while being spaced apart from the thermally conductive connection part.
9. The semiconductor package of claim 8 , wherein the electrical connection part includes:
electrically conductive pads disposed on the second surface of the interposer to be spaced apart from the thermally conductive pads;
inner wirings disposed in the interposer to electrically connect the electrically conductive pads to the first semiconductor die; and
electrically conductive connectors electrically connecting the electrically conductive pads to the stack of the second semiconductor dies, wherein the electrically conductive connectors are spaced apart from the thermally conductive connectors.
10. The semiconductor package of claim 9 , wherein each of the thermally conductive connectors and the electrically conductive connectors has a shape of a bump.
11. The semiconductor package of claim 9 , wherein the inner wirings include conductive patterns extending to be spaced apart from the thermally conductive pads and the thermally conductive vias.
12. The semiconductor package of claim 9 , wherein a first portion of the thermally conductive pads are positioned between the electrically conductive pads.
13. The semiconductor package of claim 9 , wherein a second portion of the thermally conductive pads are positioned outside the electrically conductive pads.
14. The semiconductor package of claim 1 , wherein the stack of the second semiconductor dies includes electrical through vias electrically connecting the second semiconductor dies to each other vertically.
15. The semiconductor package of claim 1 , wherein the stack of the second semiconductor dies comprises a high bandwidth memory (HBM) device including:
a base die positioned closest to the interposer among the second semiconductor dies; and
a plurality of core dies stacked substantially vertically under the base die.
16. A semiconductor package comprising:
an interposer including first and second surfaces opposite to each other;
a heat dissipation layer disposed on the first surface of the interposer;
a first semiconductor die mounted on the first surface of the interposer;
a stack of second semiconductor dies mounted on the second surface of the interposer; and
a thermally conductive connection part comprising:
a thermally conductive via penetrating through the interposer to thermally connect with the heat dissipation layer disposed on the first surface of the interposer; and
a thermally conductive connector thermally connecting the thermally conductive via to the stack of second semiconductor dies mounted on the second surface of the interposer,
wherein the interposer further includes a passivation layer exposing a surface of the heat dissipation layer on the first surface of the interposer.