Display device

1. A display device, comprising:

pixels each comprising a light emitting element, the light emitting element comprising a first electrode, an emitting layer, and a second electrode;

data lines and a dummy data line extending parallel to each other, the data lines being connected to the pixels; and

power lines and a dummy power line extending parallel to each other, the power lines being connected to the pixels,

wherein, in a plan view, each of the data lines and the power lines overlaps the first electrode of at least one of the pixels, and

wherein, in a plan view, the dummy data line and the dummy power line do not overlap the first electrode of any of the pixels.

2. The display device of claim 1 , wherein the dummy power line is connected to the power lines through a connection part extending in a second direction crossing a first direction in which the power lines extend.

3. The display device of claim 1 , wherein each of the power lines comprises:

a first power supply line parallel to the data lines; and

a second power supply line connected to the first power supply line through a contact hole passing through an insulating layer interposed between the first power supply line and the second power supply line.

4. The display device of claim 3 , wherein the second power supply line comprises first lines parallel to the data lines and second lines connecting adjacent ones of the first lines to each other.

5. The display device of claim 3 , wherein the dummy power line comprises:

a dummy first power line located at a same layer as the first power supply line; and

a dummy second power line located at a same layer as the second power supply line and electrically connected to the dummy first power line.

6. The display device of claim 5 , wherein each of the pixels further comprises a transistor connected to the light emitting element, a corresponding one of the data lines, and a corresponding one of the power lines, the transistor comprising:

an active pattern on a substrate;

source and drain electrodes each connected to the active pattern;

a gate electrode overlapping with the active pattern with a gate insulating layer interposed therebetween; and

an interlayer insulating layer covering the gate electrode, and comprising a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer, which are sequentially stacked,

wherein the first power supply line is on the second interlayer insulating layer, and

wherein the second power supply line is on the third interlayer insulating layer.

7. The display device of claim 6 , wherein each of the pixels further comprises:

a compensation transistor connected to the gate electrode of the transistor, and configured to be turned on when a scan signal is supplied to a corresponding one of scan lines to cause the transistor to be diode-connected; and

a shielding pattern on the first interlayer insulating layer, and covering at least a portion of the compensation transistor.

8. The display device of claim 7 , further comprising:

a dummy semiconductor pattern at a same layer as the active pattern, extending in parallel to the dummy data line, and connected to the dummy power line; and

a dummy shielding pattern on the first interlayer insulating layer, connected to the dummy power line, and covering at least a portion of the compensation transistor of one of the pixels.

9. The display device of claim 1 , wherein:

the pixels are located in a display area, and

the dummy data line is adjacent to an outermost pixel located at an outermost side of the display area from among the pixels.

10. The display device of claim 9 , wherein:

the outermost pixel is connected to an outermost data line of the display area from among the data lines, and

the dummy data line forms a parasitic capacitor with the outermost pixel.

11. A display device, comprising:

pixels each comprising a light emitting element;

pixel defining layer having openings which define light emitting areas of the pixels;

data lines and a dummy data line extending parallel to each other, the data lines being connected to the pixels; and

power lines and a dummy power line extending parallel to each other, the power lines being connected to the pixels,

wherein the light emitting element comprises a first electrode, an emitting layer, and a second electrode that are located in a corresponding light emitting area from among the light emitting areas,

wherein, in a plan view, each of the data lines and the power line overlaps at least one of the openings of the pixel defining layer, and

wherein, in a plan view, the dummy data line and the dummy power line do not overlap the openings of the pixel defining layer.

12. The display device of claim 11 , wherein the dummy power line is connected to the power lines through a connection part extending in a second direction crossing a first direction in which the power lines extend.

13. The display device of claim 11 , wherein each of the power lines comprises:

a first power supply line parallel to the data lines; and

a second power supply line connected to the first power supply line through a contact hole passing through an insulating layer interposed between the first power supply line and the second power supply line.

14. The display device of claim 13 , wherein the second power supply line comprises first lines parallel to the data lines and second lines connecting adjacent ones of the first lines to each other.

15. The display device of claim 13 , wherein the dummy power line comprises:

a dummy first power line located at a same layer as the first power supply line; and

a dummy second power line located at a same layer as the second power supply line and electrically connected to the dummy first power line.

16. The display device of claim 15 , wherein each of the pixels further comprises a transistor connected to the light emitting element, a corresponding one of the data lines, and a corresponding one of the power lines, the transistor comprising:

an active pattern on a substrate;

source and drain electrodes each connected to the active pattern;

a gate electrode overlapping with the active pattern with a gate insulating layer interposed therebetween; and

an interlayer insulating layer covering the gate electrode, and comprising a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer, which are sequentially stacked,

wherein the first power supply line is on the second interlayer insulating layer, and

wherein the second power supply line is on the third interlayer insulating layer.

17. The display device of claim 16 , wherein each of the pixels further comprises:

a compensation transistor connected to the gate electrode of the transistor, and configured to be turned on when a scan signal is supplied to a corresponding one of scan lines to cause the transistor to be diode-connected; and

a shielding pattern on the first interlayer insulating layer, and covering at least a portion of the compensation transistor.

18. The display device of claim 17 , further comprising:

a dummy semiconductor pattern at a same layer as the active pattern, extending in parallel to the dummy data line, and connected to the dummy power line; and

a dummy shielding pattern on the first interlayer insulating layer, connected to the dummy power line, and covering at least a portion of the compensation transistor of one of the pixels.

19. A display device, comprising:

pixels each comprising a transistor and a light emitting element connected to the transistor, the transistor comprising an active pattern;

data lines connected to the transistor of each of the pixels;

power lines connected to the transistor of each of the pixels;

a dummy data line extending parallel to the data lines;

a dummy power line extending parallel to the power lines; and

a dummy active pattern connected to the dummy data line and the dummy power line.

20. The display device of claim 19 , wherein the dummy active pattern is located at a same layer as the active pattern, and extends in parallel to the dummy data line.