Method of optimizing laser cutting of wafers for producing integrated circuit dies
A method for separating integrated circuit dies from a wafer includes making at least two cutting passes with a laser along a first die street of an integrated circuit die, the first die street extending along a first axis on the wafer. The method also includes making at least two cutting passes with the laser along a second die street of the integrated circuit die, the second die street extending along a second axis on the wafer that is generally perpendicular to the first axis. In one process, three cutting passes are made with the laser alternatingly along the first and second die streets to separate the integrated die circuit along the first and second axes. In another process, two cutting passes are made with the laser along the first die street in opposite directions, and two cutting passes are then made with the laser along the second die street in opposite directions.
1. A method of separating plurality of integrated circuit dies from a wafer, comprising:
making a first plurality of cutting passes consisting of only three cutting passes in a same first direction with a laser along a first die street of an integrated circuit die of the plurality of integrated circuit dies, the first die street extending along a first axis on the wafer; and
making a second plurality of cutting passes consisting of only three cutting passes in a same second direction with the laser along a second die street of the integrated circuit die, the second die street extending along a second axis on the wafer being generally perpendicular to the first axis, and
the first plurality of cutting passes along the first die street being altematingly and consecutively made with the second plurality of cutting passes along the second die street to thereby fully separate the integrated circuit die from the wafer along the first and second axes, the making of the first plurality and the second plurality of cutting passes with the laser along the first and second die streets on the wafer including cutting with the laser at a same power level along the first and second die streets.
2. The method of claim 1 wherein the first plurality of cutting passes along the first die street are made from an upper edge to a lower edge of the integrated circuit die.
3. The method of claim 1 wherein each of the second plurality of cutting passes along the second die street are made from a left edge to a right edge of the integrated circuit die.
4. The method of claim 1 wherein processing of the wafer to separate all integrated circuit dies on the wafer takes approximately 12 minutes.
5. The method of claim 1 wherein delamination defects in the separated integrated circuit die are reduced by approximately 90%.
6. A method of separating plurality of integrated circuit dies from a wafer, comprising:
making a first plurality of cutting passes with a laser along a first die street of an integrated circuit die of the plurality of integrated circuit dies, the first die street extending along a first axis on the wafer, the first plurality of cutting passes being only three cutting passes in a same first direction along the first axis; and
making a second plurality of cutting passes with the laser along a second die street of the integrated circuit die, the second die street extending along a second axis on the wafer being generally perpendicular to the first axis, the second plurality of cutting passes being only three cutting passes in a same second direction along the second axis,
the first plurality of cutting passes along the first die street being altematingly and consecutively made with the second plurality of cutting passes along the second die street to thereby fully separate the integrated circuit die from the wafer along the first and second axes, the making of the first plurality and the second plurality of cutting passes with the laser along the first and second die streets on the wafer including cutting with the laser at a same power level along the first and second die streets.
7. The method of claim 6 wherein each of the first plurality of cutting passes along the first die street are made from an upper edge to a lower edge of the integrated circuit die.
8. The method of claim 6 wherein each of the second plurality of cutting passes along the second die street are made from a left edge to a right edge of the integrated circuit die.
9. The method of claim 6 wherein the separating the plurality of integrated circuit dies on the wafer takes approximately 12 minutes.
10. The method of claim 1 wherein the same power level is 5.5 watts.
11. The method of claim 6 wherein the same power level is 5.5 watts.