IP Library › Granted Patent US 11,705,184
Granted Patent B2
US 11,705,184 · App. 17/849,894 · Granted Jul 18, 2023

Memory device and electronic device

Inventors: Shunpei Yamazaki (Tokyo, JP); Kiyoshi Kato (Kanagawa, JP); Takahiko Ishizu (Kanagawa, JP); Tatsuya Onuki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G11C11/4085H01L27/124H01L27/1207H01L27/1225H01L27/1255H01L29/24H01L29/7869H01L29/78648H10B99/00
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Quick Facts
Patent No.
US 11,705,184
App. No.
17/849,894
Granted
Jul 18, 2023
Kind
B2
Abstract

A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Claims (27)

1. A semiconductor device comprising:

a driver circuit;

a first negative potential generation circuit,

a second negative potential generation circuit, and

a plurality of memory cells,

wherein each memory cell comprises a transistor and a capacitor,

wherein one of a source and a drain of the transistor is electrically connected to one electrode of the capacitor,

wherein the transistor comprises a first metal oxide in a first channel formation region,

wherein the transistor comprises a first gate and a second gate,

wherein the first gate and the second gate have a region overlapping each other with the first channel formation region therebetween,

wherein the driver circuit is configured to drive the first gate,

wherein the driver circuit comprises a level shifter and a buffer,

wherein the buffer is electrically connected to a wiring,

wherein the wiring is electrically connected to the first gate,

wherein the first negative potential generation circuit has a function of supplying a first negative potential to the first gate,

wherein the second negative potential generation circuit has a function of supplying a second negative potential to the second gate.

2. The semiconductor device according to claim 1 ,

wherein the second negative potential is lower than the first negative potential.

3. The semiconductor device according to claim 1 ,

wherein the first negative potential generation circuit comprises a first ring oscillator, a first charge pump, and a first comparator,

wherein the second negative potential generation circuit comprises a second ring oscillator, a second charge pump, and a second comparator.

4. An electronic device comprising the semiconductor device according to claim 1 .

5. The semiconductor device according to claim 3 ,

wherein the first comparator comprise a second transistor,

wherein the second transistor comprises a second metal oxide in a second channel formation region,

wherein the second comparator comprise a third transistor,

wherein the third transistor comprises a third metal oxide in a third channel formation region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2022
From: YAMAZAKI, SHUNPEI; KATO, KIYOSHI; ISHIZU, TAKAHIKO; ONUKI, TATSUYA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 060318/0124 →
Priority Claims (2)
JP 2018-065571 · Mar 29, 2018 · national
JP 2018-169247 · Sep 10, 2018 · national
Continuity (2)
Continuation 17041037
Related Publication 20220328092A1 · Oct 13, 2022
Cited By (1)
US 12,205,625