Look-up table initialize
A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.
1. An integrated circuit comprising:
a processor that includes an operational unit; and
a cache coupled to the operational unit, wherein the operational unit is configured to, in response to an instruction:
provide a set of data elements to the cache;
cause the cache to duplicate the set of data elements; and
cause the cache to store a set of tables that each include a copy of the set of data elements.
2. The integrated circuit of claim 1 , wherein:
the processor includes a data register configured to store the set of data elements; and
the operational unit is configured to provide the set of data elements from the data register to the cache.
3. The integrated circuit of claim 2 , wherein:
the data register is a first data register;
the processor includes a set of data registers that includes the first data register; and
the instruction specifies the first data register from among the set of data registers.
4. The integrated circuit of claim 1 , wherein:
the instruction specifies an index at which to store the set of data elements within each table of the set of tables; and
the operational unit is configured to cause the cache to store the set of data elements within each table of the set of tables at a respective location based on the index.
5. The integrated circuit of claim 4 , wherein:
the processor includes an index register configured to store the index; and
the instruction specifies the index by specifying the index register.
6. The integrated circuit of claim 1 , wherein:
the set of tables is a first set of tables;
the cache is configured to store a plurality of sets of tables that includes the first set of tables; and
the instruction specifies the first set of tables from among the plurality of sets of tables.
7. The integrated circuit of claim 1 , wherein the processor includes a configuration register configured to store a count of tables in the set of tables.
8. The integrated circuit of claim 7 , wherein the configuration register is configured to store an element size of the set of tables.
9. The integrated circuit of claim 7 , wherein the configuration register is configured to store at least one of: a table size for each table of the set of tables, a signed-or-unsigned indicator, a promotion parameter, an interpolation parameter, a histogram weight size, or a histogram saturation parameter.
10. The integrated circuit of claim 1 , wherein the cache is a level-one (L1) cache.
11. The integrated circuit of claim 1 , wherein:
the instruction is a first instruction;
the set of data elements is a first set of data elements; and
the operational unit is configured to, in response to a second instruction:
provide a second set of data elements to the cache; and
cause the cache to store a respective data element of the set of data elements in each table of the set of tables.
12. A method comprising:
receiving a table instruction that specifies a set of data elements; and
based on the table instruction:
providing the set of data elements by a processor to a cache;
duplicating the set of data elements by the cache; and
storing a set of tables in the cache such that each table of the set of tables includes the set of data elements.
13. The method of claim 12 , wherein:
the processor includes a data register configured to store the set of data elements; and
the providing of the set of data elements includes providing the set of data elements from the data register.
14. The method of claim 13 , wherein:
the data register is a first data register;
the processor includes a set of data registers that includes the first data register; and
the table instruction specifies the first data register from among the set of data registers.
15. The method of claim 12 , wherein:
the table instruction specifies an index at which to store the set of data elements within each table of the set of tables; and
the storing of the set of tables in the cache is such the set of data elements are stored within each table of the set of tables at a respective location based on the index.
16. The method of claim 15 , wherein:
the processor includes an index register configured to store the index; and
the table instruction specifies the index by specifying the index register.
17. The method of claim 12 , wherein:
the set of tables is a first set of tables;
the cache is configured to store a plurality of sets of tables that includes the first set of tables; and
the table instruction specifies the first set of tables from among the plurality of sets of tables.
18. The method of claim 12 , wherein:
the processor includes a configuration register configured to store a count of tables in the set of tables; and
the cache is configured to store the set of tables having a number of tables based on the count of tables.
19. The method of claim 12 , wherein the cache is a level-one (L1) cache.
20. The method of claim 12 , wherein:
the table instruction is a first table instruction;
the set of data elements is a first set of data elements; and
the method further comprises:
receiving a second table instruction that specifies a second set of data elements; and
based on the second table instruction:
providing the second set of data elements by the processor to the cache; and
storing a respective data element of the second set of data elements in each table of the set of tables.