Look-up table read
A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.
1 . A device comprising:
a cache memory that includes a set of banks, wherein the cache memory is configured to store a set of table elements;
an intermediate register that includes a set of portions, wherein:
each portion of the set of portions of the intermediate register is coupled to a respective bank of the set of banks of the cache memory; and
each portion of the set of portions of the intermediate register is configured to:
receive a respective element of a first subset of the set of table elements from the respective bank; and
store the respective element of the first subset of the set of table elements;
a circuit coupled to the intermediate register and configured to:
receive a set of indices;
receive the first subset of the set of table elements from the intermediate register; and
reorder the first subset of the set of table elements based on the set of indices to produce a second subset of the set of table elements; and
a destination register coupled to the circuit and configured to store the second subset of the set of table elements.
2 . The device of claim 1 , wherein:
the set of table elements is arranged in a set of tables;
each element of the set of table elements has a respective index with respect to the set of tables; and
the set of indices corresponds to the respective index of each element of the first subset of the set of table elements with respect to the set of tables.
3 . The device of claim 2 , wherein the circuit is configured to reorder the first subset of the set of table elements based on the indices such that elements of the second subset of the set of table elements that correspond to a table of the set of tables are arranged in order based on the respective indices.
4 . The device of claim 1 , wherein the intermediate register is configured to store a first table element of the set of table elements that is received from a first bank of the set of banks adjacent to a second table element of the set of table elements that is received from a second bank of the set of banks that is adjacent to the first bank.
5 . The device of claim 4 , wherein:
the first and second subsets of the set of table elements include the first table element and the second table element; and
the circuit is configured to reorder the first subset of the set of table elements such that the first table element and the second table element are not adjacent in the destination register.
6 . The device of claim 1 , wherein:
the set of table elements is arranged as a set of tables that includes a first table and a second table;
the first subset of the set of elements includes a first portion associated with the first table and a second portion associated with the second table; and
the circuit is configured to reorder the first portion of the first subset of the set of elements and the second portion of the first subset of the set of elements independently.
7 . The device of claim 6 , wherein the circuit is configured to reorder the first portion of the first subset of the set of elements without reordering the second portion of the first subset of the set of elements.
8 . The device of claim 1 , wherein:
the set of table elements is arranged as a set of tables;
the intermediate register is configured to receive the first subset of the set of table elements from the cache memory based on an instruction; and
the instruction specifies, for each table of the set of tables, a first data element and a number of sequential data elements to retrieve from the respective table.
9 . The device of claim 8 , wherein the circuit is configured to reorder the first subset of the set of table elements such that, for each table of the set of tables, the first data element precedes the sequential data elements.
10 . The device of claim 8 further comprising a vector source index register coupled to the cache memory and configured to store, for each table of the set of tables, a respective index that specifies the first data element of the respective table.
11 . The device of claim 1 , wherein the cache memory is a level-one (L1) cache memory.
12 . An integrated circuit device comprising:
a processor;
a cache memory that includes a set of banks and that is coupled to the processor;
an intermediate register that includes a set of portions, wherein each portion of the set of portions is coupled to a respective bank of the set of banks of the cache memory;
a circuit coupled to the intermediate register; and
a destination register coupled to the circuit,
wherein the processor is configured to:
receive a first instruction;
based on the first instruction, cause the cache memory to store a set of table elements;
receive a second instruction; and
based on the second instruction:
cause the intermediate register to store a first subset of the set of table elements received from the cache memory such that each portion of the set of portions of the intermediate register stores a respective element of the first subset of the set of table elements from the respective bank;
cause the circuit to reorder the first subset of the set of table elements to produce a second subset of the set of table elements; and
cause the destination register to store the second subset of the set of table elements.
13 . The integrated circuit device of claim 12 , wherein:
the cache memory is configured to store the set of table elements arranged in a set of tables;
the integrated circuit device further comprises an index register configured to store a respective index for each table of the set of tables; and
the second instruction includes a first field that specifies the index register.
14 . The integrated circuit device of claim 13 , wherein the second instruction includes:
a second field that specifies the set of table elements; and
a third field that specifies the destination register.
15 . The integrated circuit device of claim 12 , wherein:
each table element of the set of table elements has a respective index; and
the circuit is configured to reorder the first subset of the set of table elements such that elements of the second subset that correspond to a table are arranged in order based on the respective indices.
16 . The integrated circuit device of claim 12 , wherein the intermediate register is configured to store a first table element of the set of table elements that is received from a first bank of the set of banks adjacent to a second table element of the set of table elements that is received from a second bank of the set of banks that is adjacent to the first bank.
17 . The integrated circuit device of claim 16 , wherein:
the first and second subsets of the set of table elements include the first table element and the second table element; and
the circuit is configured to reorder the first subset of the set of table elements such that the first table element and the second table element are not adjacent in the destination register.
18 . The integrated circuit device of claim 12 , wherein:
the set of table elements is arranged as a set of tables that includes a first table and a second table;
the first subset of the set of elements includes a first portion associated with the first table and a second portion associated with the second table; and
the circuit is configured to reorder the first portion of the first subset of the set of elements and the second portion of the first subset of the set of elements independently.
19 . The integrated circuit device of claim 18 , wherein the circuit is configured to reorder the first portion of the first subset of the set of elements without reordering the second portion of the first subset of the set of elements.
20 . The integrated circuit device of claim 12 , wherein the cache memory is a level-one (L1) cache memory.