Streaming engine with multi dimensional circular addressing selectable at each dimension
A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.
1. A device comprising:
a stream template register configured to store a stream template that includes a set of addressing mode indicators that includes a first addressing mode indicator for a first loop of a set of nested loops and a second addressing mode indicator for a second loop of the set of nested loops;
an address generator coupled to the stream template register to receive the set of addressing mode indicators, wherein the address generator includes:
a first control word circuit associated with the first loop and configured to, in response to the first addressing mode indicator, provide a first control word that specifies a memory block size of the respective first loop;
a first adder circuit coupled to the first control word circuit to receive the first control word and configured to circularly traverse a first memory region according to the first control word;
a second control word circuit associated with the second loop and configured to, in response to the second addressing mode indicator, provide a second control word that specifies a memory block size of the second loop; and
a second adder circuit coupled to the second control word circuit to receive the second control word and configured to circularly traverse a second memory region according to the second control word, wherein the address generator is configured to provide a set of addresses that represents the set of nested loops based on the first adder circuit and the second adder circuit; and
a memory interface coupled to the address generator to receive the set of addresses and configured to retrieve a set of data associated with the set of addresses from a memory.
2. The device of claim 1 , wherein:
the stream template further includes a first block size and a second block size; and
each of the first and second addressing mode indicators selects between either the first block size or a function of the first block size and the second block size.
3. The device of claim 2 , wherein, the first control word circuit includes:
an adder coupled to add the first block size and the second block size to provide a sum;
a multiplexer coupled to select between the first block size and the sum to provide a table index; and
a look-up table unit coupled to the multiplexer and configured to provide the respective control word in response to the table index.
4. The device of claim 3 , wherein the adder is configured to add the first block size, the second block size, and 1 to produce the sum.
5. The device of claim 2 , wherein each of the first and second addressing mode indicators further selects between: circular addressing based on the first block size, circular addressing based on the function of the first block size and the second block size, and linear addressing.
6. The device of claim 1 , wherein:
the first adder circuit is configured to perform a set of carry operations; and
the first control word specifies whether to perform the set of carry operations.
7. The device of claim 1 further comprising a stream head register coupled to the memory interface to store the set of data.
8. The device of claim 7 further comprising a processor coupled to the stream head register to receive the set of data.
9. The device of claim 8 , wherein the stream head register is configured to provide the set of data to the processor as a data stream.
10. The device of claim 8 , wherein:
the processor is configured to provide a read signal to the stream head register; and
the stream head register is configured to provide a data element of the set of data to the processor in response to the read signal.
11. The device of claim 8 , wherein:
the processor is configured to provide an advance signal to the stream head register; and
the stream head register is configured to, in response to the advance signal:
provide a first data element of the set of data to the processor; and
load a second data element of the set of data.
12. A method comprising:
receiving a template that specifies a set of addressing mode indicators that includes a first addressing mode indicator for a first loop of a set of nested loops and a second addressing mode indicator for a second loop of the set of nested loops; and
retrieving a set of data associated with the set of nested loops by:
in response to the first addressing mode indicator, providing a first control word that specifies a memory block size of the first loop;
circularly traversing a first memory region according to the first control word;
in response to the second addressing mode indicator, providing a second control word that specifies a memory block size of the second loop;
circularly traversing a second memory region according to the second control word;
generating a set of addresses based on the traversing of the first memory region and the traversing of the second memory region; and
retrieving the set of data from a memory according to the set of addresses.
13. The method of claim 12 , wherein:
the template further specifies a first block size and a second block size; and
each of the first and second addressing mode indicators selects between either the first block size or a function of the first block size and the second block size.
14. The method of claim 13 further comprising:
based on the first addressing mode indicator, selecting between the first block size and a sum of the first block size and the second block size to provide a table index; and
providing the first control word in response to the table index.
15. The method of claim 14 further comprising, adding the first block size, the second block size, and 1 to produce the sum.
16. The method of claim 13 , wherein each of the first and second addressing mode indicators further selects between: circular addressing based on the first block size, circular addressing based on the function of the first block size and the second block size, and linear addressing.
17. The method of claim 12 , wherein:
the circularly traversing of the first memory region includes performing a set of carry operations; and
the first control word specifies whether to perform the set of carry operations.
18. The method of claim 12 further comprising storing the set of data in a stream head register.
19. The method of claim 18 further comprising providing the set of data from the stream head register to a processor as a data stream.
20. The method of claim 19 further comprising:
receiving a read signal from the processor; and
providing a data element of the set of data to the processor in response to the read signal.