Streaming engine with multi dimensional circular addressing selectable at each dimension
A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.
1. A device comprising:
a first memory that stores a set of instructions that, when executed by a processor device, cause the processor device to:
store a set of values in a register that includes:
a first addressing mode value for a first loop that specifies whether to loop back to a first end of a first memory region when a second end of the first memory region is reached, wherein, when the first addressing mode value specifies to loop back to the first end of the first memory region, the set of values further specifies a size of the first memory region; and
a second addressing mode value for a second loop that specifies whether to loop back to a first end of a second memory region when a second end of the second memory region is reached, wherein, when the second addressing mode value specifies to loop back to the first end of the second memory region, the set of values further specifies a size of the second memory region; and
retrieve a set of data from a second memory based on the set of values by traversing the first memory region and the second memory region.
2. The device of claim 1 , wherein the first loop is nested within the second loop.
3. The device of claim 1 , wherein the second memory is a cache memory.
4. The device of claim 3 , wherein:
the set of instructions cause the set of values to be provided to a cache control circuit coupled to the cache memory; and
the cache control circuit is configured to retrieve the set of data from the cache memory by generating a set of addresses based on the set of values and providing the set of addresses to the cache memory.
5. The device of claim 4 , wherein:
the processor device includes the register; and
the set of instructions cause the set of values to be provided to the cache control circuit by the processor device.
6. The device of claim 4 , wherein the set of instructions cause the processor device to:
provide a read signal to the cache control circuit; and
based on the read signal, receive a data element of the set of data from the cache control circuit.
7. The device of claim 6 , wherein:
the data element is a first data element; and
the read signal specifies whether to replace the first data element in the cache control circuit with a second data element.
8. The device of claim 1 , wherein the set of instructions includes a stream open instruction that, when executed by the processor device, cause the set of data to be retrieved from the second memory.
9. The device of claim 1 , wherein the set of values includes:
a first value that specifies a first block size;
a second value that specifies a second block size; and
a third value that specifies whether the size of the first memory region is based on:
the first block size and the second block size; or
the first block size, independent of the second block size.
10. The device of claim 9 , wherein the third value specifies whether the size of the first memory region is based on a sum of the first block size, the second block size, and one.
11. The device of claim 1 further comprising:
the processor device coupled to the first memory; and
the second memory coupled to the processor device.
12. A device comprising:
a first memory configured to store a set of data;
a processor that includes a register configured to store a set of values that includes:
a first addressing mode value for a first loop that specifies whether to loop back to a first end of a first memory region when a second end of the first memory region is reached, wherein, when the first addressing mode value specifies to loop back to the first end of the first memory region, the set of values further specifies a size of the first memory region; and
a second addressing mode value for a second loop that specifies whether to loop back to a first end of a second memory region when a second end of the second memory region is reached, wherein, when the second addressing mode value specifies to loop back to the first end of the second memory region, the set of values further specifies a size of the second memory region;
a memory control circuit coupled between the processor and the first memory; and
a second memory configured to store a set of instructions, that when executed by the processor, cause the processor to cause the memory control circuit to provide the set of data from the first memory to the processor based on the set of values by traversing the first memory region and the second memory region.
13. The device of claim 12 , wherein the first loop is nested within the second loop.
14. The device of claim 12 , wherein the first memory is a cache memory.
15. The device of claim 12 , wherein:
the set of instructions cause the processor to provide the set of values to the memory control circuit; and
the memory control circuit is configured to retrieve the set of data from the first memory by generating a set of addresses based on the set of values and providing the set of addresses to the first memory.
16. The device of claim 15 , wherein the set of instructions cause the processor to:
provide a read signal to the memory control circuit; and
based on the read signal, receive a data element of the set of data from the memory control circuit.
17. The device of claim 16 , wherein:
the data element is a first data element; and
the read signal specifies whether to replace the first data element in the memory control circuit with a second data element.
18. The device of claim 12 , wherein the set of values includes:
a first value that specifies a first block size;
a second value that specifies a second block size; and
a third value that specifies whether the size of the first memory region is based on:
the first block size and the second block size; or
the first block size, independent of the second block size.
19. The device of claim 18 , wherein the third value specifies whether the size of the first memory region is based on a sum of the first block size, the second block size, and one.
20. A method comprising:
storing a set of values in a register of a processor, wherein the set of values includes:
a first addressing mode value for a first loop that specifies whether to loop back to a first end of a first memory region when a second end of the first memory region is reached, wherein, when the first addressing mode value specifies to loop back to the first end of the first memory region, the set of values further specifies a size of the first memory region; and
a second addressing mode value for a second loop that specifies whether to loop back to a first end of a second memory region when a second end of the second memory region is reached, wherein, when the second addressing mode value specifies to loop back to the first end of the second memory region, the set of values further specifies a size of the second memory region; and
in response to an instruction:
providing the set of values from the processor to a memory control circuit; and
retrieving, using the memory control circuit, a set of data from a memory based on the set of values by traversing the first memory region and the second memory region.