Semiconductor memory device with 3D structure

1. A semiconductor memory device with a three-dimensional (3D) structure, comprising:

a cell region arranged over a substrate, including a cell structure, wherein the cell structure includes a plurality of cell gate conductive films and a plurality of insulation films alternately stacked over the substrate;

a peripheral circuit region arranged between the substrate and the cell region;

an upper wiring structure arranged over the cell region;

main channel films and dummy channel films formed through the cell structure, wherein the dummy channel films are suitable for electrically coupling the upper wiring structure and the peripheral circuit region;

bit lines disposed over the cell structure and electrically coupled to the main channel films;

dummy bit lines disposed over the cell structure and electrically coupled to the dummy channel films;

an upper wiring layer disposed over the bit lines and the dummy bit lines, and electrically coupled to the dummy bit lines; and

a common source line formed at the same layer as the bit lines and the dummy bit lines,

wherein the main channel films and the dummy channel films extend above an uppermost film of the plurality of cell gate conductive films and the plurality of insulation films of the cell structure relative to the substrate, and

wherein the dummy bit lines are disposed between the bit lines and the common source line,

wherein the upper wiring structure further comprises:

an external connection pad disposed over the upper wiring layer, and electrically coupled to the upper wiring layer.

2. The semiconductor memory device of claim 1 , wherein the peripheral circuit region comprises:

peripheral circuit elements; and

a lower wiring structure suitable for electrically coupling the peripheral circuit elements and the dummy channel films.

3. The semiconductor memory device of claim 2 , wherein the upper wiring structure is formed of a conductive material having lower resistance than the lower wiring structure.

4. The semiconductor memory device of claim 2 , further comprising vertical contacts suitable for electrically coupling the dummy channel films and the lower wiring structure.

5. The semiconductor memory device of claim 4 , further comprising a semiconductor pattern disposed between the peripheral circuit region and the cell region and having an opening through which the vertical contacts are passed.

6. The semiconductor memory device of claim 5 , wherein the opening overlaps the dummy channel films.

7. The semiconductor memory device of claim 5 , wherein the semiconductor pattern comprises a common source region electrically coupled to the main channel films.