Semiconductor device

1. A semiconductor device, comprising:

a substrate;

channel semiconductor patterns stacked on the substrate and vertically spaced apart from each other;

a gate electrode crossing the channel semiconductor patterns;

source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces toward top surfaces of the source/drain regions; and

air gaps between the substrate and the bottom surfaces of the source/drain regions,

wherein topmost portions of the air gaps are located at a level lower than a bottom surface of a lowermost one of the channel semiconductor patterns.

2. The device as claimed in claim 1 , wherein:

the source/drain regions are spaced apart from each other in a first direction,

each of the source/drain regions includes a pair of first semiconductor patterns, which are spaced apart from each other in the first direction, and

the pair of first semiconductor patterns have lower portions and upper portions, widths of the lower portions in the first direction being larger than widths of the upper portions in the first direction.

3. The device as claimed in claim 1 , wherein:

the source/drain regions are spaced apart from each other in a first direction, and

each of the source/drain regions includes:

a pair of first semiconductor patterns, which are spaced apart from each other in the first direction, and

a second semiconductor pattern on the pair of first semiconductor patterns and connecting the pair of first semiconductor patterns.

4. The device as claimed in claim 3 , wherein:

the channel semiconductor patterns include a first semiconductor element,

each first semiconductor pattern of the pair of first semiconductor patterns and the second semiconductor pattern include a second semiconductor element, a lattice constant of the second semiconductor element being greater than a lattice constant of the first semiconductor element, and

a content of the second semiconductor element in the second semiconductor pattern is higher than a content of the second semiconductor element in each first semiconductor pattern.

5. The device as claimed in claim 3 , wherein the topmost portions of the air gaps are defined by a bottom surface of each second semiconductor pattern.

6. The device as claimed in claim 3 , wherein each of the air gaps is between the pair of first semiconductor patterns.

7. The device as claimed in claim 1 , wherein:

the channel semiconductor patterns include a first semiconductor element,

the source/drain regions include the first semiconductor element and a second semiconductor element, a lattice constant of the second semiconductor element being greater than a lattice constant of the first semiconductor element, and

a content of the second semiconductor element in the source/drain regions decreases with decreasing distance from the substrate.

8. The device as claimed in claim 1 , wherein:

the source/drain regions are spaced apart from each other in a first direction,

each of the source/drain regions includes a pair of first semiconductor patterns spaced apart from each other in the first direction, and

bottommost portions of the first semiconductor patterns are located at a level lower than the bottom surface of the lowermost one of the channel semiconductor patterns.

9. The device as claimed in claim 1 , wherein:

the source/drain regions include:

a first semiconductor pattern covering side surfaces of the channel semiconductor patterns, and

a second semiconductor pattern on the first semiconductor pattern, and

the topmost portions of the air gaps are defined by a bottom surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern.

10. The device as claimed in claim 1 , wherein a width of each of the air gaps increases with decreasing distance from the substrate.

11. A semiconductor device, comprising:

a substrate;

a first channel semiconductor pattern on the substrate and at a first vertical level;

a second channel semiconductor pattern stacked on the first channel semiconductor pattern and located at a second vertical level higher than the first vertical level;

a gate electrode crossing the first channel semiconductor pattern and the second channel semiconductor pattern, the gate electrode extending in a first direction; and

a source/drain region on a side surface of the gate electrode and connected to the first channel semiconductor pattern and the second channel semiconductor pattern,

wherein:

the source/drain region includes:

a first semiconductor pattern covering side surfaces of the first channel semiconductor pattern and the second channel semiconductor pattern; and

a second semiconductor pattern on the first semiconductor pattern,

the first semiconductor pattern having a first width in a second direction perpendicular to the first direction at the first vertical level,

the first semiconductor pattern having a second width in the second direction at the second vertical level, and

the first width is greater than the second width.

12. The device as claimed in claim 11 , wherein:

each of the first channel semiconductor pattern and the second channel semiconductor pattern includes a first semiconductor element and a second semiconductor element,

a lattice constant of the second semiconductor element is greater than a lattice constant of the first semiconductor element, and

a content of the second semiconductor element in the second semiconductor pattern is higher than a content of the second semiconductor element in the first semiconductor pattern.

13. The device as claimed in claim 11 , wherein a bottommost portion of the first semiconductor pattern is located at a level lower than a bottom surface of the first channel semiconductor pattern.

14. The device as claimed in claim 11 , further comprising an air gap between the substrate and a bottom surface of the source/drain region.

15. The device as claimed in claim 14 , wherein a topmost portion of the air gap is located at a level lower than a bottom surface of the first channel semiconductor pattern.

16. The device as claimed in claim 14 , wherein a width of the air gap in the second direction increases with decreasing distance from the substrate.

17. The device as claimed in claim 11 , wherein the gate electrode fills a space between the first and second channel semiconductor patterns.

18. The device as claimed in claim 11 , further comprising an active contact on the source/drain region and connected to the second semiconductor pattern.

19. The device as claimed in claim 11 , wherein:

the first semiconductor pattern includes a pair of first semiconductor patterns that are spaced apart from each other in the second direction, and

the second semiconductor patter connects the pair of first semiconductor patterns to each other.

20. The device as claimed in claim 19 , wherein:

the pair of first semiconductor patterns each include a protruding portion, and

the protruding portion of one first semiconductor pattern protrudes toward the protruding portion of another first semiconductor pattern.