Semiconductor memory device
A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
1. A semiconductor memory device comprising:
a first memory cell array that includes a plurality of first memory cells, each of the first memory cells capable of being set into one of n threshold voltage levels, n being an integer of 4 or more;
a first word line connected to gates of the first memory cells;
a plurality of first sense amplifiers connected to the first memory cells, respectively;
a second memory cell array that includes a plurality of second memory cells, each of the second memory cells capable of being set into one of n threshold voltage levels;
a second word line connected to gates of the second memory cells;
a plurality of second sense amplifiers connected to the second memory cells, respectively;
a control circuit configured to perform a read operation to read data from the first memory cells and from the second memory cells; and
an input/output circuit connected to the first sense amplifiers and to the second sense amplifiers, wherein
upon receipt of a first read command associated with a first page address,
the control circuit applies i different voltages to the first word line, and j different voltages to the second word line, i being an integer of 1 or more, j being an integer larger than i, and
upon receipt of a second read command associated with a second page address,
the control circuit applies k different voltages to the second word line, and I different voltages to the first word line, k being an integer of 1 or more, I being an integer larger than k.
2. The semiconductor memory device according to claim 1 , wherein
the first sense amplifiers read data from the first memory cells, respectively,
the second sense amplifiers read data from the second memory cells, respectively,
in response to the first read command, the first sense amplifiers transfer the data read from the first memory cells to the input/output circuit, and thereafter the second sense amplifiers transfer the data read from the second memory cells to the input/output circuit, and
in response to the second read command, the second sense amplifiers transfer the data read from the second memory cells to the input/output circuit, and thereafter the first sense amplifiers transfer the data read from the first memory cells to the input/output circuit.
3. The semiconductor memory device according to claim 2 , wherein
in response to the first read command, the first sense amplifiers start transferring the data read from the first memory cells to the input/output circuit while one of the j different voltages is applied to the second word line, and
in response to the second read command, the second sense amplifiers start transferring the data read from the second memory cells to the input/output circuit, while one of the I different voltages is applied to the first word line.
4. The semiconductor memory device according to claim 3 , wherein
in response to a first data out command after the first read command, the input/output circuit starts outputting the data transferred from the first sense amplifiers, while one of the j different voltages is applied to the second word line, and
in response to a second data out command after the second read command, the input/output circuit starts outputting the data transferred from the second sense amplifiers, while one of the I different voltages is applied to the first word line.
5. The semiconductor memory device according to claim 1 , wherein
the input/output circuit receives the first read command and the second read command in sequence, and the second read command is received while the read response in response to the first read command is being executed.
6. The semiconductor memory device according to claim 1 , wherein
in response to a first write command associated with the first page address, the control circuit divides write data into two parts, and writes the two parts of the write data into the first memory cells and the second memory cells, respectively.
7. The semiconductor memory device according to claim 1 , wherein the input/output circuit includes:
a logical-to-physical address conversion circuit configured to convert a logical address of the first page address associated with the first read command or the second page address associated with the second read command into a physical address of the first memory cells and a physical address of the second memory cells.
8. The semiconductor memory device according to claim 7 , wherein
the logical-to-physical address conversion circuit is further configured to convert the first read command or a second read command into a first internal read command for the first memory cells and a second internal read command for the second memory cells.
9. The semiconductor memory device according to claim 1 , wherein i equals k and j equals I.
10. A method of operating a semiconductor memory device comprising:
a first memory cell array that includes a plurality of first memory cells, each of the first memory cells capable of being set into one of n threshold voltage levels, n being an integer of 4 or more;
a first word line connected to gates of the first memory cells;
a plurality of first sense amplifiers connected to the first memory cells, respectively;
a second memory cell array that includes a plurality of second memory cells, each of the second memory cells capable of being set into one of n threshold voltage levels;
a second word line connected to gates of the second memory cells;
a plurality of second sense amplifiers connected to the second memory cells, respectively; and
an input/output circuit connected to the first sense amplifiers and to the second sense amplifiers,
said method comprising:
upon receipt of a first read command associated with a first page address,
applying i different voltages to the first word line, and j different voltages to the second word line, i being an integer of 1 or more, j being an integer larger than i; and
upon receipt of a second read command associated with a second page address,
applying k different voltages to the second word line, and I different voltages to the first word line, k being an integer of 1 or more, I being an integer larger than k.
11. The method according to claim 10 , wherein
the first sense amplifiers read data from the first memory cells, respectively,
the second sense amplifiers read data from the second memory cells, respectively,
in response to the first read command, the first sense amplifiers transfer the data read from the first memory cells to the input/output circuit, and thereafter the second sense amplifiers transfer the data read from the second memory cells to the input/output circuit, and
in response to the second read command, the second sense amplifiers transfer the data read from the second memory cells to the input/output circuit, and thereafter the first sense amplifiers transfer the data read from the first memory cells to the input/output circuit.
12. The method according to claim 11 , wherein
in response to the first read command, the first sense amplifiers start transferring the data read from the first memory cells to the input/output circuit while one of the j different voltages is applied to the second word line, and
in response to the second read command, the second sense amplifiers start transferring the data read from the second memory cells to the input/output circuit, while one of the I different voltages is applied to the first word line.
13. The method according to claim 12 , wherein
in response to a first data out command after the first read command, the input/output circuit starts outputting the data transferred from the first sense amplifiers, while one of the j different voltages is applied to the second word line, and
in response to a second data out command after the second read command, the input/output circuit starts outputting the data transferred from the second sense amplifiers, while one of the I different voltages is applied to the first word line.
14. The method according to claim 10 , wherein
the input/output circuit receives the first read command and the second read command in sequence, and the second read command is received while the read response in response to the first read command is being executed.
15. The method according to claim 10 , further comprising:
in response to a first write command associated with the first page address, dividing write data into two parts, and writing the two parts of the write data into the first memory cells and the second memory cells, respectively.
16. The method according to claim 10 , further comprising:
converting a logical address of the first page address associated with the first read command or the second page address associated with the second read command into a physical address of the first memory cells and a physical address of the second memory cells.
17. The method according to claim 16 , further comprising:
converting the first read command or a second read command into a first internal read command for the first memory cells and a second internal read command for the second memory cells.
18. The method according to claim 10 , wherein i equals k and j equals I.