FeFET of 3D structure for capacitance matching
An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.
1. A method of manufacturing an integrated circuit (IC) comprising a MFMIS-FET, the method comprising:
forming a semiconductor fin over a substrate;
forming a dummy gate stack over and on two sides of the semiconductor fin;
patterning the dummy gate stack to define a dummy gate;
forming a sidewall spacer around the dummy gate;
etching away a portion of the dummy gate to create a void region flanked by the sidewall spacers; and
after creating the void region, performing a series of depositions that comprise depositing a high-κ dielectric, a metal gate, a ferroelectric layer, and a top electrode layer, wherein the series of depositions fill the void region.
2. The method of claim 1 , wherein
depositing the high-κ dielectric and the metal gate fills the void region and the method further comprises:
after depositing the metal gate, recessing the metal gate below a height of the sidewall spacer to form a recess,
wherein the forming a ferroelectric layer and the top electrode layer are deposited within the recess.
3. The method of claim 1 , wherein the dummy gate is formed over a plurality of semiconductor fins.
4. The method of claim 1 , further comprising:
etching the top electrode layer below a height of the sidewall spacer to form a second recess; and
filling the second recess to form an etch stop layer over the top electrode layer.
5. The method of claim 1 , further comprising:
before etching away a portion of the dummy gate, filling a space around the sidewall spacer with an interlevel dielectric;
etching to recess the interlevel dielectric below a height of the sidewall spacer to form a recess; and
filling the recess with a dielectric to form an etch stop layer.
6. A method of manufacturing an integrated circuit (IC), the method comprising:
forming a dummy gate stack including a dummy gate electrode layer;
patterning the dummy gate stack to form dummy gates;
forming sidewall spacers around the dummy gates;
replacing the dummy gate electrode layer of the dummy gates with a first metal layer;
planarizing an upper surface of the first metal layer;
etching to recess the first metal layer to below a height of the sidewall spacers; and
depositing a ferroelectric layer and a top electrode layer directly over the first metal layer.
7. The method of claim 6 , further comprising planarizing an upper surface of the top electrode layer to align with an upper surface of the sidewall spacers.
8. The method of claim 7 , further comprising:
etching the upper surface of the top electrode layer below the height of the sidewall spacers to form a second recess; and
filling the second recess with dielectric.
9. The method of claim 6 , wherein the dummy gates have a FinFET or gate-all-around structure.
10. The method of claim 6 , wherein the dummy gates each comprise a plurality of semiconductor fins.
11. The method of claim 6 , further comprising:
before replacing the dummy gate electrode layer, filling around the sidewall spacers with an interlevel dielectric;
etching to recess the interlevel dielectric below a height of the sidewall spacers to form recesses; and
filling the recesses with a dielectric to form an etch stop layer.
12. The method of claim 6 , wherein the first metal layer comprises a layer of a work functional metal and a layer of a second metal.
13. A method of manufacturing an integrated circuit (IC), the method comprising:
forming dummy gates having FinFET or gate-all-around structure; and
replacing the dummy gates with a high-k dielectric, a first electrode layer, a ferroelectric layer, and a second electrode layer according to a process that includes chemical mechanical polishing of an upper surface of the first electrode layer followed by recessing the upper surface by etching.
14. The method of claim 13 , wherein the ferroelectric layer and second electrode layer are formed within a recess formed by the recessing the upper surface.
15. The method of claim 13 , wherein the dummy gates comprise a plurality of semiconductor fins.
16. The method of claim 13 , further comprising:
forming sidewall spacers around the dummy gates;
wherein the chemical mechanical polishing aligns the upper surface with tops of the sidewall spacers.
17. The method of claim 16 , further comprising:
etching to recess the second electrode layer below the tops of the sidewall spacers to form recesses; and
filling the recesses with a dielectric.
18. The method of claim 13 , wherein the dummy gates each comprise a plurality of semiconductor fins.
19. The method of claim 16 , further comprising:
before replacing the dummy gates, filling a space around the sidewall spacers with an interlevel dielectric;
etching to recess the interlevel dielectric below a height of the sidewall spacers to form recesses; and
filling the recesses to form an etch stop layer.
20. The method of claim 13 , wherein the first electrode layer comprises a layer of a work functional metal and a layer of a second metal.