Nanowire stack GAA device with inner spacer and methods for producing the same
A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
1. A method of forming a semiconductor device, the method comprising:
forming a first fin structure over a substrate, the first fin structure including alternating layers of a first semiconductor material layer and a second semiconductor material layer;
forming a gate structure over the first fin structure;
forming a receded strip by removing portions of a topmost layer of the second semiconductor material layer on opposing sides of the gate structure, wherein, after forming the receded strip, a lower layer of the second semiconductor material layer has a first length, wherein a second length of the receded strip is less than the first length, wherein the lower layer of the second semiconductor material layer is below the topmost layer of the second semiconductor material layer;
forming receded sacrificial strips by removing portions of the first semiconductor material layers on opposing sides of the gate structure, the receded sacrificial strips each including recessed edge surfaces;
forming an inner spacer adjacent to the recessed edge surfaces of the receded sacrificial strips; and
epitaxially growing a source/drain structure adjacent to the inner spacer and remaining portions of the alternating layers of the first semiconductor material layer and the second semiconductor material layer.
2. The method of claim 1 , wherein the source/drain structure extends around remaining ones of the second semiconductor material layers.
3. The method of claim 1 , wherein after epitaxially growing the source/drain structure a void is interposed between the source/drain structure and at least one of the receded sacrificial strips.
4. The method of claim 1 , further comprising:
removing the gate structure;
removing the receded sacrificial strips in a channel region; and
forming a replacement gate structure around remaining ones of the second semiconductor material layers.
5. The method of claim 4 , wherein after forming the replacement gate structure a void is interposed between the source/drain structure and the replacement gate structure.
6. The method of claim 1 , wherein the source/drain structure directly contacts the receded strip.
7. The method of claim 1 , wherein forming the inner spacer comprises:
forming a dielectric layer adjacent to the receded sacrificial strips and the receded strip;
forming an etch stop layer selectively covering first portions of the dielectric layer adjacent the receded sacrificial strips;
removing second portions of the dielectric layer free of the etch stop layer; and
removing the etch stop layer.
8. A method of forming a semiconductor device, the method comprising:
forming a first fin structure over a substrate, the first fin structure including alternating layers of a first semiconductor material and a second semiconductor material;
forming a gate structure over the first fin structure;
forming a first receded strip by removing portions of a topmost layer of the second semiconductor material on opposing sides of the gate structure;
forming receded sacrificial strips by removing portions of the first semiconductor material on opposing sides of the gate structure, the receded sacrificial strips each including recessed edge surfaces;
forming an inner spacer layer adjacent to the recessed edge surfaces of the receded sacrificial strips, the inner spacer layer extending over upper surfaces of at least a first layer of the second semiconductor material, the first layer being below the topmost layer of the second semiconductor material;
forming etch stop portions over the inner spacer layer adjacent the recessed edge surfaces of the receded sacrificial strips, exposed portions of the inner spacer layer extending away from the etch stop portions;
removing the exposed portions of the inner spacer layer, remaining portions of the inner spacer layer forming inner spacers; and
forming a source/drain structure adjacent to the inner spacer and the layers of the second semiconductor material.
9. The method of claim 8 , wherein forming the source/drain structure comprises:
epitaxially growing a semiconductor material around the layers of the second semiconductor material.
10. The method of claim 8 , wherein the source/drain structure directly contacts the first receded strip.
11. The method of claim 8 , wherein forming the source/drain structure forms a void between the source/drain structure and the receded sacrificial strips.
12. The method of claim 8 , further comprising:
removing the gate structure;
removing at least portions of the receded sacrificial strips; and
forming a replacement gate structure adjacent the layers of the second semiconductor material.
13. The method of claim 12 , wherein a width of the replacement gate structure is less than a width of the first receded strip.
14. The method of claim 8 , further comprising, prior to forming the receded sacrificial strips, forming a second receded strip by removing portions of a topmost layer of the first semiconductor material on opposing sides of the gate structure.
15. A method of forming a semiconductor device, the method comprising:
forming a first fin structure over a substrate, the first fin structure including alternating layers of a first semiconductor material and a second semiconductor material;
forming a gate structure over the first fin structure;
forming receded sacrificial strips by removing portions of the first semiconductor material on opposing sides of the gate structure, the receded sacrificial strips each including recessed edge surfaces;
forming an inner spacer layer adjacent to the recessed edge surfaces of the receded sacrificial strips and over the layers of the second semiconductor material;
forming etch stop portions over the inner spacer layer adjacent the recessed edge surfaces of the receded sacrificial strips;
removing exposed portions of the inner spacer layer, remaining portions of the inner spacer layer forming inner spacers adjacent the recessed edge surfaces of the receded sacrificial strips; and
forming a source/drain structure adjacent to the inner spacer and the layers of the second semiconductor material.
16. The method of claim 15 , prior to forming the inner spacer layer, forming a first receded strip by removing portions of an uppermost layer of the alternating layers.
17. The method of claim 15 , prior to forming the inner spacer layer, forming a first receded strip and a second receded strip by removing portions of uppermost layers of the first semiconductor material and the second semiconductor material.
18. The method of claim 15 , further comprising:
removing the gate structure;
removing at least portions of the receded sacrificial strips; and
forming a replacement gate structure adjacent the layers of the second semiconductor material, wherein a void is interposed between the source/drain structure and the replacement gate structure.
19. The method of claim 18 , wherein the void is interposed between the source/drain structure and the inner spacers.
20. The method of claim 18 , wherein after forming the replacement gate structure the void is interposed between the source/drain structure and the inner spacers.