Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

1. A method of fabricating a power grid (PG) arrangement in a semiconductor device, the method comprising:

forming a first layer including lines (C_1st lines) that extend in a first direction and are conductive, the C_1st lines including:

alpha ones of the C_1st lines (alpha C_1st lines) designated for a first reference voltage and beta ones of the C_1st (beta C_1st lines) designated for a second reference voltage;

the alpha and beta C_1st lines being interspersed relative to a second direction perpendicular to the first direction; and

forming a second layer over the first layer, the second layer including segments (C_2nd segments) that extend in the second direction and are conductive, the C_2nd segments including:

alpha ones of the C_2nd segments (alpha C_2nd segments) designated for the first reference voltage and beta ones of the C_2nd segments (beta C_2nd segments) designated for the second reference voltage;

the alpha and beta C_2nd segments being interspersed relative to the first direction; and

relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.

2. The method of claim 1 , wherein:

relative to the first direction, all beta C_2nd segments have substantially the same asymmetric relationship between corresponding adjacent ones of the alpha C_2nd segments which represents a repeating asymmetric pitch pattern of the second layer.

3. The method of claim 2 , wherein:

the second layer has Φ [V1(1)˜V2(1)]:[V2(1)˜V1(2)] as the repeating asymmetric pitch pattern, where:

V1(1) represents a first given one of the alpha C_2nd segments;

V2(1) represents a first given one of the beta C_2nd segments; and

V1(2) represents a second given one of the alpha C_2nd segments;

V1(1) and V1(2) are correspondingly left and right adjacent to V2(1); and Φ [V1(1)˜V2(1)]:[V2(1)˜V1(2)] is as follows:

Φ [V1(1)˜V2(1)]:[V2(1)˜V1(2)] =3λ:4λ,

where:

λ represents a base distance such that

λ= k*CPP,

where:

k is a positive integer; and

CPP represents a contacted polysilicon pitch of a corresponding semiconductor process/technology node.

4. The method of claim 3 , wherein:

k=4 such that Φ (V2L˜V1C):(V1C˜V2R) is as follows:

Φ (V2L˜V1C):(V1C˜V2R) =12 CPP: 16 CPP.

5. The method of claim 2 , wherein:

the second layer has Φ [V1(1)˜V2(1)]:[V2(1)˜V1(2)]:[V1(2)˜V2(2)]:[V2(2)˜V1(3)] as the repeating asymmetric pitch pattern, where:

V1(1) represents a first given one of the alpha C_2nd segments;

V2(1) represents a first given one of the beta C_2nd segments; and

V1(2) represents a second given one of the alpha C_2nd segments; and

V2(2) represents a second given one of the beta C_2nd segments; and

V1(3) represents a third given one of alpha C_2nd segments;

V1(1) and V1(2) are correspondingly left and right adjacent to V2(1);

V2(1) and V2(2) are correspondingly left and right adjacent to V1(2);

V1(2) and V1(3) are correspondingly left and right adjacent to V2(2); and

Φ [V1(1)˜V2(1)]:[V2(1)˜V1(2)]:[V1(2)˜V2(2)]:[V2(2)˜V1(3)] is as follows:

Φ [V1(1)˜V2(1)]:[V2(1)˜V1(2)]:[V1(2)˜V2(2)]:[V2(2)˜V1(3)] =4λ:3λ:3λ:4λ;

where:

λ represents a base distance such that

λ= k*CPP;

where:

k being a positive integer; and

CPP representing a contacted polysilicon pitch of a corresponding semiconductor process/technology node.

6. The method of claim 5 , wherein:

k=4 such that Φ [V1(1)˜V2(1)]:[V2(1)˜V1(2)]:[V1(2)˜V2(2)]:[V2(2)˜V1(3)] is as follows:

Φ [V1(1)˜V2(1)]:[V2(1)˜V1(2)]:[V1(2)˜V2(2)]:[V2(2)˜V1(3)] =16 CPP: 12 CPP: 12 CPP: 16 CPP.

7. The method of claim 1 , wherein the forming a first layer includes:

depositing substantially parallel lines of conductive material;

selectively removing portions of the lines, remaining portions of the lines being the alpha C_2nd segments and beta C_2nd segments, each of the alpha and beta C_2nd segments a short-pillar length, the short-pillar length being approximately a minimum length of C_2nd segment for a corresponding semiconductor process/technology node.

8. The method of claim 1 , wherein:

the forming a first layer includes:

depositing substantially parallel lines of conductive material; and

selectively removing portions of the lines, remaining portions of the lines being the alpha C_2nd segments and beta C_2nd segments;

each of the alpha and beta C_2nd segments has a short-pillar length;

the short-pillar length is approximately a minimum length of a C_2nd segment for a corresponding semiconductor process/technology node; and

relative to the second direction, each beta C_1st line is substantially symmetrically between corresponding adjacent ones of the alpha C_1st lines.

9. The method of claim 1 , wherein:

the forming a second layer includes:

depositing lines of conductive material which are substantially parallel, the lines including alpha C_2nd precursor lines and beta C_2nd precursor lines;

relative to the first direction, each beta channel being substantially asymmetrically between corresponding adjacent ones of the alpha channels;

for any given segments alpha C_2nd precursor line (given alpha C_2nd precursor line) and any given one of the beta C_2nd precursor line (given beta C_2nd precursor line) which is adjacent to the given alpha C_2nd precursor line, a distance between the given alpha C_2nd precursor line and the given beta C_2nd precursor line is a multiple of a base distance X such that

λ= k*CPP;

k being a positive integer; and

CPP representing a contacted polysilicon pitch of a corresponding semiconductor process/technology node.

10. The method of claim 1 , wherein the forming a second layer includes:

forming a layer of insulating material;

forming channels in the layer of insulating material, the channels being substantially straight and substantially parallel;

the channels including alpha channels and beta beta channels;

relative to the first direction, each beta channel being substantially asymmetrically between corresponding adjacent ones of the alpha channels;

depositing conductive material in the alpha and beta channels resulting alpha C_2nd precursor lines and beta C_2nd precursor lines; and

selectively removing portions of the alpha and beta precursor lines, remaining portions of the lines being the alpha C_2nd and beta C_2nd segments.

11. A method of fabricating a power grid (PG) in a semiconductor device, the method comprising:

forming a first layer including lines (C_1st lines) that extend in a first direction and are conductive, the C_1st lines including:

alpha ones of the C_1st lines (alpha C_1st lines) designated for a first reference voltage and beta ones of the C_1st (beta C_1st lines) designated for a second reference voltage;

the alpha and beta C_1st lines being interspersed relative to a second direction perpendicular to the first direction; and

forming a second layer over the first layer, the second layer including segments (C_2nd segments) that extend in the second direction and are conductive, the C_2nd segments including:

alpha ones of the C_2nd segments (alpha C_2nd segments) designated for the first reference voltage and beta ones of the C_2nd segments (beta C_2nd segments) designated for the second reference voltage;

the alpha and beta C_2nd segments being interspersed relative to the first direction; and

relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments; and

for any given one of alpha C_2nd segments (given alpha C_2nd segment) and any given one of the beta C_2nd segments (given beta C_2nd segment) which is adjacent to the given alpha C_2nd segment, a distance between the given alpha C_2nd segment and the given beta C_2nd segment is both a multiple of four and a multiple of CPP, where CPP represents a contacted polysilicon pitch of a corresponding semiconductor process/technology node.

12. The method of claim 11 , wherein:

relative to the first direction, all beta C_2nd segments have substantially the same asymmetric relationship between corresponding adjacent ones of the alpha C_2nd segments which represents a repeating asymmetric pitch pattern of the second layer.

13. The method of claim 11 , wherein the forming a first layer includes:

depositing substantially parallel lines of conductive material; and

selectively removing portions of the lines, remaining portions of the lines being the alpha C_2nd and beta C_2nd segments, each of the alpha and beta C_2nd segments a short-pillar length, the short-pillar length being approximately a minimum length of C_2nd segment for a corresponding semiconductor process/technology node.

14. The method of claim 11 , wherein the forming a first layer includes:

depositing substantially parallel lines of conductive material; and

selectively removing portions of the lines, remaining portions of the lines being the alpha C_1st and beta C_2nd lines, each of the alpha and beta C_2nd segments a short-pillar length, the short-pillar length being approximately a minimum length of C_2nd segment for a corresponding semiconductor process/technology node; and

relative to the second direction, each beta C_1st line being substantially symmetrically between corresponding adjacent ones of the alpha C_1st lines.

15. The method of claim 11 , wherein the forming a second layer includes:

forming a layer of insulating material;

forming channels in the layer of insulating material, the channels being substantially straight and substantially parallel;

the channels including alpha channels and beta beta channels;

relative to the first direction, each beta channel being substantially asymmetrically between corresponding adjacent ones of the alpha channels;

depositing conductive material in the alpha and beta channels resulting alpha C_2nd precursor lines and beta C_2nd precursor lines; and

selectively removing portions of the alpha and beta precursor lines, remaining portions of the lines being the alpha C_2nd and beta C_2nd segments.

16. A method of fabricating a power grid (PG) arrangement in a semiconductor device comprising:

forming a first layer including lines (C_1st lines) that extend in a first direction and are conductive, the C_1st lines including:

alpha ones of the C_1st lines (alpha C_1st lines) designated for a first reference voltage and beta ones of the C_1st (beta C_1st lines) designated for a second reference voltage;

the alpha and beta C_1st lines being interspersed relative to a second direction perpendicular to the first direction; and

forming a second layer over the first layer, the second layer including segments (C_2nd segments) that extend in the second direction and are conductive, the C_2nd segments including:

alpha ones of the C_2nd segments (alpha C_2nd segments) designated for the first reference voltage and beta ones of the C_2nd segments (beta C_2nd segments) designated for the second reference voltage;

the alpha and beta C_2nd segments being interspersed relative to the first direction; and

relative to cross-sections of the alpha C_1st lines and beta C_1st lines which are oriented perpendicularly to corresponding long axes thereof, cross-sectional electrical resistances of the alpha C_1st lines and beta C_1st lines are substantially the same;

the alpha C_2nd segments have a first pitch;

the beta C_2nd segments have the first pitch;

for each of the alpha C_1st lines and beta C_1st lines, a length thereof substantially equal to the first pitch has an electrical resistance referred to as a stub resistance; and

the first pitch is sized to keep a stub resistance below a threshold resistance.

17. The method of claim 16 , wherein:

the first pitch is P X3&4 ;

the alpha C_1st lines have a second pitch P Y1&2 ; and

the beta C_1st lines have the second pitch P Y1&2 ; and

a ratio of the second pitch P Y1&2 to the first pitch P X3&4 is

ratio=( P Y1&2 )/( P X3&4 )≈¼.

18. The method of claim 17 , wherein:

the ratio of the second pitch P Y1&2 to the first pitch P X3&4 is

ratio=( P Y1&2 )/( P X3&4 )≈8.4 CPP/ 30 CPP,

where CPP represents a contacted polysilicon pitch of a corresponding semiconductor process/technology node.

19. The method of claim 16 , wherein:

the alpha C_1st lines have a second pitch;

the beta C_1st lines have the second pitch; and

the first pitch is smaller than the first pitch.

20. The method of claim 16 , wherein:

an arrangement of the C_2nd segments in the conductive layer is substantially asymmetric relative to the first direction such that:

each alpha C_2nd segment is substantially asymmetrically between corresponding adjacent ones of the beta C_2nd segments; and

each beta C_2nd segment is substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.