Semiconductor package including test pad and bonding pad structure for die connection and methods for forming the same
A semiconductor package structure includes a first die, a second die disposed on the first die, and a bonding pad structure. The first die includes a semiconductor substrate, an interconnect structure disposed on the first semiconductor substrate, a passivation layer disposed on the interconnect structure, and a test pad disposed on the passivation layer. The test pad includes a contact region that extends through the passivation layer and electrically contacts the interconnect structure, and a bonding recess that overlaps with the contact region in a vertical direction perpendicular to a plane of the first semiconductor substrate. The bonding pad structure electrically connects the first die and the second die and directly contacts at least a portion of the bonding recess.
1. A semiconductor package comprising:
a first die comprising:
a first semiconductor substrate;
a first interconnect structure disposed on the first semiconductor substrate;
a first passivation layer disposed on the first interconnect structure; and
a test pad disposed on the first passivation layer, the test pad comprising a contact region that extends through the first passivation layer and electrically contacts the first interconnect structure, and a bonding recess that overlaps with the contact region in a vertical direction perpendicular to a plane of the first semiconductor substrate;
a second die stacked on the first die in the vertical direction; and
a bonding pad structure electrically connecting the first die and the second die and directly contacting at least a portion of the bonding recess.
2. The semiconductor package of claim 1 , wherein the bonding pad structure directly contacts from 0.1% to 100% of the bonding recess.
3. The semiconductor package of claim 1 , wherein the bonding pad structure directly contacts from 50% to 100% of the bonding recess.
4. The semiconductor package of claim 1 , wherein the bonding pad structure comprises:
a bonding via structure that directly contacts the bonding recess; and
a bonding pad that is disposed on the bonding via structure and is electrically connected to the second die.
5. The semiconductor package of claim 4 , further comprising a die bonding structure comprising:
a first bonding layer that covers the first die; and
a second bonding layer that covers the second die and is bonded to the first die.
6. The semiconductor package of claim 5 , wherein:
the bonding via structure extends through the first bonding layer and an interconnect planarization layer; and
the bonding pad extends through the second bonding layer and contacts a second interconnect structure of the second die.
7. The semiconductor package of claim 1 , wherein the test pad comprises:
a landing region disposed on the first passivation layer, over the contact region, the landing region comprising the bonding recess; and
a test region disposed on the first passivation layer and extending from the landing region.
8. The semiconductor package of claim 7 , wherein the test region is wider than the landing region and is configured to contact a test probe.
9. The semiconductor package of claim 1 , wherein the test pad is formed of a material having a higher electrical resistance than a material used to form the bonding pad structure.
10. The semiconductor package of claim 1 , wherein:
the test pad comprises aluminum or an aluminum alloy; and
the bonding pad structure comprises copper, gold, silver, or a combination thereof.
11. The semiconductor package of claim 1 , wherein the bonding recess has a concave surface and is configured to decrease electrical contact resistance between the test pad and the bonding pad structure.
12. The semiconductor package of claim 1 , wherein the first die and the second die are face-to-face bonded.
13. A semiconductor package comprising:
a first die comprising:
a first semiconductor substrate;
a first interconnect structure disposed on the first semiconductor substrate;
a first passivation layer disposed on the first interconnect structure; and
a first test pad disposed on the first passivation layer, the first test pad comprising a first contact region that extends through the first passivation layer and electrically contacts the first interconnect structure, and a first bonding recess that overlaps with the first contact region in a vertical direction perpendicular to a plane of the first semiconductor substrate;
a second die stacked on the first die in the vertical direction and comprising:
a second semiconductor substrate;
a second interconnect structure disposed on the second semiconductor substrate;
a second passivation layer disposed on the second interconnect structure; and
a second test pad disposed on the second passivation layer, the second test pad comprising a second contact region that extends through the second passivation layer and electrically contacts the second interconnect structure, and a second bonding recess that overlaps with the second contact region in the vertical direction; and
a bonding pad structure that electrically connects the first die and the second die and directly contacts least a portion of the first bonding recess and at least a portion of the second bonding recess.
14. The semiconductor package of claim 13 , wherein the bonding pad structure directly contacts from 0.1% to 100% of a surface of the first bonding recess and directly contacts from 0.1% to 100% of a surface of the second bonding recess.
15. The semiconductor package of claim 13 , wherein the bonding pad structure comprises:
a first bonding via structure that directly contacts the first bonding recess;
a second bonding via structure that directly contacts the second bonding recess; and
a bonding pad that connects the first bonding via structure and the second bonding via structure.
16. The semiconductor package of claim 15 , further comprising a die bonding structure comprising a first bonding layer bonded to the first die and a second bonding layer bonded to the second die and the first bonding layer,
wherein the bonding pad comprises:
a first metal layer formed in the first bonding layer and bonded to the first bonding via structure; and
a second metal layer formed in the second bonding layer and bonded to the second bonding via structure and the first metal layer.
17. The semiconductor package of claim 13 , wherein:
the first die and the second die are face-to-face bonded; and
the first test pad and the second test pad are formed of a material having a higher electrical resistance than a material used to form the bonding pad structure.
18. A method of forming a semiconductor package, comprising:
forming a first trench in a first passivation layer of a first die to expose a first interconnect structure of the first die;
forming a first test pad on the first passivation layer and in the first trench, such that the first test pad comprises a first bonding recess disposed above the first trench;
forming a first planarization layer on the first test pad and forming a first bonding layer on the first planarization layer;
forming a second trench in the first bonding layer and the first planarization layer to expose the first bonding recess;
forming a bonding via structure in the second trench, such that the bonding via structure directly contacts at least a portion of the first bonding recess; and
bonding a second die to the first die, such that a second bonding layer disposed on the second die is bonded to the first bonding layer and a bonding pad of the second die is bonded to the bonding via structure to form a bonding pad structure that electrically connects the first die and the second die.
19. The method of claim 18 , wherein the bonding via structure directly contacts from 0.1% to 100% of the first bonding recess.
20. The method of claim 18 , wherein:
bonding the first die to the second die comprises face-to-face bonding; and
forming the first test pad comprises forming the first test pad of a material having a higher electrical resistance than a material used to form the bonding pad structure.