Caching of logical-to-physical mapping information in a memory sub-system

1. A system comprising:

a memory device; and

a processing device coupled to the memory device, the processing device comprising a primary flash translation layer (FTL) and a secondary FTL, the primary FTL configured to perform operations comprising:

receiving a request specifying a logical address associated with a host-initiated operation directed at a first portion of the memory device; and

providing a look-up request to the secondary FTL based on the request, the look-up request specifying the logical address;

the secondary FTL configured to perform operations comprising:

accessing, from a volatile memory component, a logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device;

identifying an entry in the L2P table that corresponds to the logical address;

determining the entry in the L2P table points to an entry in a read cache table;

calculating a chunk address corresponding to a chunk from among multiple chunks of a read cache based on a combination of an entry number of the entry in the read cache table, a unit size of chunks in the read cache, and the logical address associated with the host-initiated operation directed at the first portion of the memory device, the chunk in the read cache storing information that specifies a physical address within the first portion of the memory device that corresponds to the logical address specified by the request;

identifying, based on the chunk of the read cache corresponding to the chunk address, a physical address that corresponds to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of memory device; and

providing the physical address to the primary FTL responsive to the look-up request, the primary FTL further configured to execute the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.

2. The system of claim 1 , wherein the chunk size corresponds to an indirection size of the L2P table.

3. The system of claim 1 , wherein the calculating of the chunk address comprises:

adding the logical address to a result of multiplying the entry number by the chunk size.

4. The system of claim 1 , wherein:

the L2P table is a first L2P table; and

the second portion of the memory device stores a second L2P table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device.

5. The system of claim 4 , wherein:

the request is a first request;

the logical address is a first logical address;

the host-initiated operation is a first host-initiated operation;

the entry is a first entry; and

the operations further comprise:

receiving a second request specifying a second logical address associated with a second host-initiated operation directed at the first portion of a memory device;

identifying a second entry in the first L2P table that corresponds to the second logical address;

accessing a portion of the second L2P table from the second portion of the memory device identified based on the second entry in the first L2P table; and

adding the accessed portion of the second L2P table to the read cache based on determining the entry in the first L2P table does not point to the read cache table.

6. The system of claim 5 , wherein the operations further comprise:

adding a new entry to the read cache table corresponding to the accessed portion of the first L2P table added to the read cache.

7. The system of claim 6 , wherein adding the new entry to the read cache table comprises:

randomly selecting an existing entry in the read cache table; and

replacing the existing entry in the read cache table with the new entry corresponding to the accessed portion of the first L2P table added to the read cache.

8. The system of claim 5 , wherein the operations further comprise:

identifying, based on the first L2P table, a physical location within the second portion of the memory device that corresponds to the portion of the second L2P table that specifies a second physical address within the first portion of the memory device that corresponds to the second logical address; and

identifying, based on the portion of the second L2P table, the second physical address within the first portion of the memory device that corresponds to the second logical address specified by the second request; and

performing the second host-initiated operation at the second physical address within the first portion of the memory device.

9. The system of claim 1 , wherein:

the memory device is a NAND memory device;

the first portion comprises multiple quad-level cells (QLCs); and

the second portion comprises multiple single level cells (SLCs).

10. The system of claim 1 , wherein the host-initiated operation comprises one of: a read operation, a write operation, or an erase operation.

11. The system of claim 1 , wherein the volatile memory component comprises one of: dynamic random-access memory (DRAM) or holographic random-access memory (HRAM).

12. A method comprising:

receiving, by a primary flash translation layer (FTL) of a memory sub-system controller, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device;

providing, by the primary FTL, a look-up request to a secondary FTL of the memory sub-system controller based on the request, the look-up request specifying the logical address;

accessing, by the secondary FTL, from a volatile memory component, a logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device;

identifying by the secondary FTL, an entry in the L2P table that corresponds to the logical address;

based on determining the entry in the L2P table points to an entry in a read cache table, calculating, by the secondary FTL, a chunk address corresponding to a chunk from among multiple chunks of a read cache based on a combination of an entry number of the entry in the read cache table a unit size of chunks in the read cache, and the logical address specified in the request, the chunk in the read cache storing information that specifies a physical address within the first portion of the memory device that corresponds to the logical address specified by the request;

identifying, by the secondary FTL, a physical address that corresponds to the logical address specified by the request based on the chunk of the read cache corresponding to the chunk address, the physical address corresponding to a physical location in the first portion of memory device;

providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request; and

performing, by the primary FTL, the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.

13. The method of claim 12 , wherein the chunk size corresponds to an indirection size of the L2P table.

14. The method of claim 12 , wherein the calculating of the chunk address comprises:

adding the logical address to a result of multiplying the entry number by the chunk size.

15. The method of claim 12 , wherein:

the L2P table is a first L2P table; and

the second portion of the memory device stores a second L2P table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device.

16. The method of claim 15 , wherein:

the request is a first request;

the logical address is a first logical address;

the host-initiated operation is a first host-initiated operation;

the entry is a first entry; and

the operations further comprise:

receiving a second request specifying a second logical address associated with a second host-initiated operation directed at the first portion of a memory device;

identifying a second entry in the first L2P table that corresponds to the second logical address;

accessing a portion of the second L2P table from the second portion of the memory device identified based on the second entry in the first L2P table; and

adding the accessed portion of the second L2P table to the read cache based on determining the entry in the first L2P table does not point to the read cache table.

17. The method of claim 16 , wherein the operations further comprise:

adding a new entry to the read cache table corresponding to the accessed portion of the first L2P table added to the read cache.

18. The method of claim 17 , wherein adding the new entry to the read cache table comprises:

randomly selecting an existing entry in the read cache table; and

replacing the existing entry in the read cache table with the new entry corresponding to the accessed portion of the first L2P table added to the read cache.

19. The method of claim 16 , wherein the operations further comprise:

identifying, based on the first L2P table, a physical location within the second portion of the memory device that corresponds to the portion of the second L2P table that specifies a second physical address within the first portion of the memory device that corresponds to the second logical address; and

identifying, based on the portion of the second L2P table, the second physical address within the first portion of the memory device that corresponds to the second logical address specified by the second request; and

performing the second host-initiated operation at the second physical address within the first portion of the memory device.

20. A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising:

receiving, by a primary flash translation layer (FTL) of the processing device, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device;

providing, by the primary FTL, a look-up request to a secondary FTL of the processing device based on the request, the look-up request specifying the logical address;

accessing, by the secondary FTL, from a volatile memory component, a logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device;

determining, by the secondary FTL, an entry in the L2P table that corresponds to the logical address points to an entry in a read cache table;

calculating, by the secondary FTL, a chunk address corresponding to a chunk from among multiple chunks of a read cache based on a combination of an entry number of the entry in the read cache table, a unit size of chunks in the read cache, and the logical address associated with the host-initiated operation directed at the first portion of the memory device, the chunk in the read cache storing information that specifies a physical address within the first portion of the memory device that corresponds to the logical address specified by the request;

accessing, by the secondary FTL, from the volatile memory component, the chunk of the read cache corresponding to the chunk address;

identifying, by the secondary FTL, based on the chunk of the read cache corresponding to the chunk address, a physical address that corresponds to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of memory device;

providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request; and

performing, by the primary FTL, the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.