Storing a logical-to-physical mapping in NAND memory
A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.
1 . A system comprising:
a memory device comprising a first portion and a second portion, the second portion storing a first logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device; and
a processing device coupled to the memory device, the processing device comprising a primary flash translation layer (FTL) and a secondary FTL, the primary FTL configured to perform operations comprising:
receiving a request specifying a logical address associated with a host-initiated operation directed at the first portion of the memory device;
providing a look-up request to the secondary FTL based on the request, the look-up request specifying the logical address;
the secondary FTL configured to perform operations comprising:
identifying, based on the first L2P table, the physical address within the first portion of the memory device that corresponds to the logical address; and
providing the physical address to the primary FTL responsive to the look-up request, the primary FTL further configured to execute the host-initiated operation at the physical address within the first portion of the memory device that corresponds to the logical address specified by the request.
2 . The system of claim 1 , wherein:
the physical address within the first portion of the memory device is a first physical address;
the operations comprise identifying a second physical address corresponding to a physical location within the second portion of the memory device, the physical location within the second portion of the memory device corresponding to a portion of the first L2P table that specifies the first physical address.
3 . The system of claim 2 , wherein the operations further comprise:
accessing the portion of the first L2P table from the physical location within the second portion of the memory device.
4 . The system of claim 3 , further comprising a read cache comprising multiple chunks to cache portions of the first L2P table, wherein the operations further comprise adding the accessed portion of the first L2P table to the read cache based on determining an entry in a second L2P table does not point to the read cache table.
5 . The system of claim 4 , wherein a size of each chunk in the multiple chunks corresponds to an indirection unit size of the second L2P table.
6 . The system of claim 5 , wherein:
the indirection size of the second L2P table is a first indirection unit size;
the first L2P table uses a second indirection unit size.
7 . The system of claim 6 , wherein the first indirection unit size is smaller than the second indirection unit size.
8 . The system of claim 4 , wherein the second L2P table is stored in one of: dynamic random-access memory (DRAM) or holographic random-access memory (HRAM).
9 . The system of claim 1 , wherein the operations further comprise adding a new entry to a read cache table that is logically linked to a chunk of read cache in which the portion of the first L2P table is cached, wherein the adding of the new entry to the read cache table comprises:
randomly selecting an existing entry in the read cache table; and
replacing the existing entry in the read cache table with the new entry.
10 . The system of claim 1 , wherein the host-initiated operation comprises one of: a read operation, a write operation, or an erase operation.
11 . A method comprising:
receiving, at a primary flash translation layer (FTL) of a memory sub-system controller, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device, the memory device comprising the first portion and a second portion, the second portion storing a first logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device;
providing, by the primary FTL, a look-up request to a secondary FTL of the memory sub-system controller based on the request, the look-up request specifying the logical address;
identifying, by the secondary FTL, based on the first L2P table, the physical address within the first portion of the memory device that corresponds to the logical address;
providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request; and
performing, by the primary FTL, the host-initiated operation at the physical address within the first portion of the memory device that corresponds to the logical address specified by the request.
12 . The method of claim 11 , wherein:
the physical address within the first portion of the memory device is a first physical address;
the method comprises identifying a second physical address corresponding to a physical location within the second portion of the memory device, the physical location within the second portion of the memory device corresponding to a portion of the first L2P table that specifies the first physical address.
13 . The method of claim 12 , further comprising a read cache comprising multiple chunks to cache portions of the first L2P table, wherein the operations further comprise adding the portion of the first L2P table to the read cache based on determining an entry in a second L2P table does not point to the read cache table.
14 . The method of claim 13 , wherein a size of each chunk in the multiple chunks corresponds to an indirection size of the second L2P table.
15 . The method of claim 14 , wherein:
the indirection size of the second L2P table is a first indirection unit size;
the first L2P table uses a second indirection unit size.
16 . The method of claim 15 , wherein the first indirection unit size is smaller than the second indirection unit size.
17 . The method of claim 13 , wherein the second L2P table is stored in one of: dynamic random-access memory (DRAM) or holographic random-access memory (HRAM).
18 . The method of claim 11 , further comprising adding a new entry to a read cache table that is logically linked to a chunk of read cache in which the portion of the first L2P table is cached, wherein the adding of the new entry to the read cache table comprises:
randomly selecting an existing entry in the read cache table; and
replacing the existing entry in the read cache table with the new entry.
19 . The method of claim 11 , wherein the host-initiated operation comprises one of: a read operation, a write operation, or an erase operation.
20 . A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising:
receiving, at a primary flash translation layer (FTL) of a memory sub-system controller, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device, the memory device comprising the first portion and second portion, the second portion storing a first logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device;
providing, by the primary FTL, a look-up request to a secondary FTL of the memory sub-system controller based on the request, the look-up request specifying the logical address;
identifying, by the secondary FTL, based on the first L2P table, the physical address within the first portion of the memory device that corresponds to the logical address;
providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request; and
performing, by the primary FTL, the host-initiated operation at the physical address within the first portion of the memory device that corresponds to the logical address specified by the request.