Microelectronic package with solder array thermal interface material (SA-TIM)
Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.
1. A microelectronic package, comprising:
a package substrate;
a die coupled with the package substrate at a first face of the die;
a plurality of solder thermal interface material (STIM) thermal interconnects coupled with the die at a second face of the die in a two-dimensional array pattern, wherein the second face is opposite the first face;
an integrated heat spreader (IHS) coupled with the plurality of STIM thermal interconnects; and
a thermal underfill material positioned between the IHS and the die, wherein the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects.
2. The microelectronic package of claim 1 , further comprising a patterning layer between the IHS and a STIM thermal interconnect of the plurality of STIM thermal interconnects.
3. The microelectronic package of claim 1 , further comprising a solder resist layer coupled to the second face of the die and adjacent to, and at least partially surrounding, a STIM thermal interconnect of the plurality of STIM thermal interconnects.
4. The microelectronic package of claim 1 , further comprising a solder resist layer coupled to the IHS and adjacent to, and at least partially surrounding, a STIM thermal interconnect of the plurality of STIM thermal interconnects.
5. The microelectronic package of claim 1 , wherein a first STIM thermal interconnect of the plurality of STIM thermal interconnects has a different size or shape than a second STIM thermal interconnect of the plurality of STIM thermal interconnects.
6. The microelectronic package of claim 1 , wherein a distance between the second face of the die and the IHS is less than 150 micrometers.
7. A microelectronic package, comprising:
a die coupled with a package substrate;
a plurality of solder thermal interface material (STIM) thermal interconnects coupled with a face of the die, wherein the plurality of STIM thermal interconnects are at least partially surrounded by a thermal underfill material;
an integrated heat spreader (IHS) coupled with the first plurality of STIM thermal interconnects, wherein the die is between the IHS and the package substrate and a distance between the die and the IHS is less than 150 micrometers; and
a spacer physically coupled with the IHS and the package substrate.
8. The microelectronic package of claim 7 , wherein the spacer is to stiffen an outer periphery of the IHS.
9. The microelectronic package of claim 7 , wherein the spacer is to provide a mechanical load bearing spacing between the IHS and the package substrate.
10. The microelectronic package of claim 7 , wherein the spacer includes steel, copper, aluminum, or polymer.
11. The microelectronic package of claim 7 , wherein the spacer is a first spacer, the microelectronic package further includes a second spacer adjacent to the first spacer, and the second spacer is physically coupled with the IHS and the package substrate.
12. The microelectronic package of claim 7 , wherein the spacer is a solder ball.
13. The microelectronic package of claim 7 , wherein the plurality of STIM thermal interconnects have a z-height of less than 50 micrometers.
14. The microelectronic package of claim 7 , wherein a first STIM thermal interconnect of the plurality of STIM thermal interconnects has a different size or shape than a second STIM thermal interconnect of the plurality of STIM thermal interconnects.
15. A microelectronic package, comprising:
a first die coupled with a package substrate;
a second die coupled with the package substrate;
a first plurality of solder thermal interface material (STIM) thermal interconnects coupled with the first die;
a second plurality of STIM thermal interconnects coupled with the second die;
an integrated heat spreader (IHS) coupled with the first plurality of STIM thermal interconnects and the second plurality of STIM thermal interconnects;
a first thermal underfill material between the IHS and the first die, wherein the first thermal underfill material at least partially surrounds the first plurality of STIM thermal interconnects; and
a second thermal underfill material between the IHS and the second die, wherein the second thermal underfill material at least partially surrounds the second plurality of STIM thermal interconnects.
16. The microelectronic package of claim 15 , wherein the second plurality of STIM thermal interconnects have a same z-height as measured in a direction perpendicular to a face of the second die to which they are coupled as a z-height of the first plurality of STIM thermal interconnects.
17. The microelectronic package of claim 15 , wherein the second plurality of STIM thermal interconnects have a different z-height as measured in a direction perpendicular to a face of the second die to which they are coupled as a z-height of the first plurality of STIM thermal interconnects.
18. The microelectronic package of claim 15 , wherein the first plurality of STIM thermal interconnects are coupled with the first die in a two-dimensional array pattern.
19. The microelectronic package of claim 18 , wherein the two-dimensional array pattern is a grid pattern.
20. The microelectronic package of claim 18 , wherein the two-dimensional array pattern is a randomized pattern.