Integrated fan-out package having stress release structure
A semiconductor package includes a redistribution structure, a first die, a second die and a buffer layer. The second die is disposed between the first die and the redistribution structure, and the second die is electrically connected to the first die and bonded to the redistribution structure. The buffer layer is disposed on a first sidewall of the second die, wherein a second sidewall of the buffer layer is substantially flush with a third sidewall of the first die.
1. A semiconductor package, comprising:
a redistribution structure;
a first die and a second die between the first die and the redistribution structure, the second die electrically connected to the first die and bonded to the redistribution structure; and
a buffer layer, disposed on a first sidewall of the second die, wherein a second sidewall opposite to the first sidewall of the second die is exposed by the buffer layer.
2. The semiconductor package according to claim 1 , wherein the second sidewall of the second die is flush with a sidewall of the first die.
3. The semiconductor package according to claim 1 , wherein the second die comprises a substrate, and a Young's modulus of the buffer layer is smaller than a Young's modulus of the substrate.
4. The semiconductor package according to claim 1 further comprising a third die between the first die and the second die, wherein the buffer layer is further disposed on a sidewall of the third die.
5. The semiconductor package according to claim 4 , wherein a width of a portion of the buffer layer on the second die is different from a width of a portion of the buffer layer on the third die.
6. The semiconductor package according to claim 1 , wherein a surface of the buffer layer is flush with a surface of the second die.
7. The semiconductor package according to claim 1 , wherein a sidewall of the buffer layer is flush with a sidewall of the first die.
8. A semiconductor package, comprising:
a redistribution structure;
a first die and a second die stacked on each other, the second die bonded to the redistribution structure;
a buffer layer, disposed on a first vertical sidewall of the second die and extended onto a first portion of a second vertical sidewall of the first die without extending between the first die and the second die; and
an underfill being in contact with the buffer layer and a second portion of the second vertical sidewall of the first die.
9. The semiconductor package according to claim 8 , wherein the buffer layer has a ring-shaped pattern surrounding the second die.
10. The semiconductor package according to claim 8 , wherein the buffer layer is further disposed on a third vertical sidewall opposite to the first vertical sidewall of the second die.
11. The semiconductor package according to claim 8 , wherein a third vertical sidewall opposite to the first vertical sidewall of the second die is flush with a fourth vertical sidewall opposite to the second vertical sidewall of the first die.
12. The semiconductor package according to claim 8 , wherein a Young's modulus of the buffer layer is in a range of 200 MPa to 100 GPa, and coefficient of thermal expansion of the buffer layer is in a range of 0 ppm/° C. to 20 ppm/° C.
13. The semiconductor package according to claim 8 further comprising a third die bonded to the redistribution structure and encapsulated by the underfill partially, wherein the buffer layer is disposed between the second die and the third die.
14. A semiconductor package, comprising:
a redistribution structure bonded to a substrate;
a first package comprising a first die and a second die, bonded to the redistribution structure between the first package and the substrate;
a second package bonded to the redistribution structure, wherein the redistribution structure is a continuous structure disposed continuously under the first package and the second package;
a first buffer layer, disposed on a sidewall of the second die; and
a second buffer layer, disposed on a sidewall of the second package, wherein the first buffer layer and the second buffer layer are disposed between the first package and the second package.
15. The semiconductor package according to claim 14 further comprising an underfill between the first package and the redistribution structure and between the first buffer layer and the second package, wherein the underfill is in direct contact with a sidewall of the first die.
16. The semiconductor package according to claim 14 further comprising an encapsulant encapsulating the first package and the second package, wherein a sidewall of the encapsulant is flush with a sidewall of the redistribution structure.
17. The semiconductor package according to claim 14 , wherein the first buffer layer surrounds the first package.
18. The semiconductor package according to claim 14 , wherein the first buffer layer is in direct contact with the second die.
19. The semiconductor package according to claim 14 , wherein the second package comprises a third die, and the second buffer layer is in direct contact with a sidewall of the third die.
20. The semiconductor package according to claim 14 , wherein a sidewall of the first buffer layer is flush with a sidewall of the first die.