Memory device architecture coupled to a system-on-chip
The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.
1. An apparatus, comprising:
a plurality of sub arrays of memory cells;
sense amplifiers coupled to a corresponding sub array of the plurality of sub arrays; and
a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers, wherein each JTAG cell of the plurality of JTAG cells includes:
a parallel input (PIN) terminal and a serial input (SIN) terminal; and
a parallel output terminal (POUT) and a serial output terminal (SOUT); and
wherein the plurality of JTAG cells form a scan-chain, and wherein:
the PIN terminal of a first JTAG cell is coupled to an output of a first sense amplifier;
the POUT terminal of the first JTAG cell is coupled to a corresponding data input/output terminal;
the SIN terminal of the first JTAG cell is coupled to the SOUT terminal of a second JTAG cell; and
the SOUT terminal of the first JTAG cell is coupled to the SIN terminal of a third JTAG cell.
2. The apparatus of claim 1 , wherein the corresponding data input/output terminal is a terminal of a System-on-Chip (SoC).
3. The apparatus of claim 1 , wherein the apparatus is a memory device, and wherein the scan-chain forms a single shift register for testing an interconnection between pads of the memory device and corresponding pads of the SoC.
4. The apparatus of claim 1 , wherein the memory device is a non-volatile memory device.
5. The apparatus of claim 1 , wherein the first JTAG cell comprises at least four latches.
6. The apparatus of claim 5 , wherein the first JTAG cell comprises at least two multiplexers.
7. The apparatus of claim 1 , wherein the first JTAG cell comprises:
an input multiplexer;
a first pair of latches;
an output multiplexer between the first pair of latches; and
a second pair of latches.
8. The apparatus of claim 1 , wherein the apparatus comprises a memory component structurally independent from a System-on-Chip (SoC) to which it is coupled.
9. The apparatus of claim 8 , wherein the memory component partially overlaps the SoC.
10. The apparatus of claim 8 , wherein the memory component is coupled to the SoC in a face-to-face manner.
11. An apparatus, comprising:
a plurality of sub arrays of memory cells;
sense amplifiers coupled to a corresponding sub array of the plurality of sub arrays; and
a plurality of scan-chain cells forming a scan-chain, wherein the plurality of scan-chain cells are coupled to outputs of the sense amplifiers, and wherein each scan-chain cell of the plurality of scan-chain cells includes:
a parallel input (PIN) terminal and a serial input (SIN) terminal; and
a parallel output terminal (POUT) and a serial output terminal (SOUT); and wherein:
the PIN terminal of a first scan-chain cell is coupled to an output of a first sense amplifier;
the POUT terminal of the first scan-chain cell is coupled to a corresponding data input/output terminal;
the SIN terminal of the first scan-chain cell is coupled to the SOUT terminal of a second scan-chain cell; and
the SOUT terminal of the first scan-chain cell is coupled to the SIN terminal of a third scan-chain cell.
12. The apparatus of claim 11 , wherein each scan-chain cell of the plurality of scan-chain cells comprises:
a JTAG cell; and
a first additional latch.
13. The apparatus of claim 12 , wherein each scan-chain cell of the plurality of scan-chain cells further comprises a second additional latch.
14. The apparatus of claim 12 , wherein the PIN terminal of the first scan-chain cell is coupled to the first additional latch of the first scan-chain cell and to a first multiplexer of the first scan-chain cell.
15. The apparatus of claim 11 , wherein the first scan-chain cell comprises a JTAG cell, a first additional latch, and a second additional latch, and wherein an output of the first additional latch is provided to an input of the second additional latch.
16. The apparatus of claim 15 , wherein the PIN terminal of the first scan-chain cell is coupled to the first additional latch and to a first multiplexer of the first scan-chain cell.
17. The apparatus of claim 16 , wherein an output of the second additional latch is provided to an input of a second multiplexer of the first scan-chain cell.
18. An apparatus, comprising:
a plurality of sub arrays of memory cells;
sense amplifiers coupled to a corresponding sub array of the plurality of sub arrays; and
a plurality of scan-chain cells forming a scan-chain, wherein the plurality of scan-chain cells are coupled to outputs of the sense amplifiers, and wherein each scan-chain cell of the plurality of scan-chain cells includes:
a parallel input (PIN) terminal coupled to a first latch and to a first multiplexer;
a serial input (SIN) terminal coupled to the first multiplexer;
a second latch coupled to an output of the multiplexer;
a serial output terminal (SOUT) coupled to an output of the second latch, wherein the output of the second latch is provided to a third latch; and
a parallel output terminal (POUT) coupled to an output of a second multiplexer, wherein the second multiplexer receives, as inputs, an output from the third latch and an output from a fourth latch.
19. The apparatus of claim 18 , wherein an input of the fourth latch is coupled to an output of the first latch.
20. The apparatus of claim 18 , wherein each scan-chain cell of the plurality of scan-chain cells comprises a JTAG cell.