IP Library › Granted Patent US 11,749,373
Granted Patent B2
US 11,749,373 · App. 17/732,023 · Granted Sep 5, 2023

Bad block management for memory sub-systems

Inventor: Roland J. Awusie (Boise, ID)
Assignee: Micron Technology, Inc.
G11C29/44G11C29/38G11C11/5621G11C16/0483
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Quick Facts
Patent No.
US 11,749,373
App. No.
17/732,023
Granted
Sep 5, 2023
Kind
B2
Abstract

A first pool of blocks of a memory device is determined, wherein blocks of the first pool are associated with storing system data at a single bit per memory cell. A second pool of blocks of the memory device is determined, wherein blocks of the second pool are associated with storing user data at a plurality of bits per memory cell. In response to detecting a failure associated with a particular block of the second pool of blocks, the particular block is added to the first pool of blocks.

Claims (55)

1. A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to perform operations comprising:

determining a first pool of blocks of the memory device, wherein blocks of the first pool are associated with storing system data at a single bit per memory cell;

determining a second pool of blocks of the memory device, wherein blocks of the second pool are associated with storing user data at a plurality of bits per memory cell; and

in response to detecting a failure associated with a particular block of the second pool of blocks, adding the particular block to the first pool of blocks.

2. The system of claim 1 , further comprising:

detecting the failure associated with the particular block, wherein detecting the failure comprises determining that a number of errors associated with the particular block satisfies a threshold error criterion.

3. The system of claim 2 , wherein detecting the failure associated with the particular block further comprises:

determining that reading the particular block at the plurality of bits per memory cell has failed to retrieve a stored data at the particular block.

4. The system of claim 1 , wherein adding the particular block to the first pool of blocks comprises:

erasing data stored at the particular block from the second pool of blocks; and

adding the particular block to the first pool of blocks in response to erasing the data.

5. The system of claim 1 , wherein the processing device to perform operations further comprising:

receiving user data;

generating system data of a memory sub-system associated with the memory device;

storing the user data to a block from the second pool of blocks at the plurality of bits per memory cell; and

storing the system data to a block from the first pool of blocks at the single bit per memory cell.

6. The system of claim 5 , wherein storing the system data to the block from the first pool of blocks at the single bit per memory cell further comprises storing the system data at a single-level cell (SLC) mode, and wherein storing the user data to the block from the second pool of blocks at the plurality of bits per memory cell further comprises storing the user data by using a programming operation that stores a plurality of bits per each memory cell.

7. The system of claim 5 , wherein the system data corresponds to a characteristic of the memory sub-system at a time when the user data is stored at the memory sub-system.

8. A method comprising:

determining a first pool of blocks of a memory device, wherein blocks of the first pool are associated with storing system data at a single bit per memory cell;

determining a second pool of blocks of the memory device, wherein blocks of the second pool are associated with storing user data at a plurality of bits per memory cell; and

in response to detecting a failure associated with a particular block of the second pool of blocks, adding the particular block to the first pool of blocks.

9. The method of claim 8 , further comprising:

detecting the failure associated with the particular block, wherein detecting the failure comprises determining that a number of errors associated with the particular block satisfies a threshold error criterion.

10. The method of claim 9 , wherein detecting the failure associated with the particular block further comprises:

determining that reading the particular block at the plurality of bits per memory cell has failed to retrieve a stored data at the particular block.

11. The method of claim 8 , wherein adding the particular block to the first pool of blocks comprises:

erasing data stored at the particular block from the second pool of blocks; and

adding the particular block to the first pool of blocks in response to erasing the data.

12. The method of claim 8 , further comprising:

receiving user data;

generating system data of a memory sub-system associated with the memory device;

storing the user data to a block from the second pool of blocks at the plurality of bits per memory cell; and

storing the system data to a block from the first pool of blocks at the single bit per memory cell.

13. The method of claim 12 , wherein storing the system data to the block from the first pool of blocks at the single bit per memory cell further comprises storing the system data at a single-level cell (SLC) mode, and wherein storing the user data to the block from the second pool of blocks at the plurality of bits per memory cell further comprises storing the user data by using a programming operation that stores a plurality of bits per each memory cell.

14. The method of claim 12 , wherein the system data corresponds to a characteristic of the memory sub-system at a time when the user data is stored at the memory sub-system.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

determining a first pool of blocks of a memory device, wherein blocks of the first pool are associated with storing system data at a single bit per memory cell;

determining a second pool of blocks of the memory device, wherein blocks of the second pool are associated with storing user data at a plurality of bits per memory cell; and

in response to detecting a failure associated with a particular block of the second pool of blocks, adding the particular block to the first pool of blocks.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is to perform operations further comprising:

detecting the failure associated with the particular block, wherein detecting the failure comprises determining that a number of errors associated with the particular block satisfies a threshold error criterion.

17. The non-transitory computer-readable storage medium of claim 16 , wherein detecting the failure associated with the particular block further comprises:

determining that reading the particular block at the plurality of bits per memory cell has failed to retrieve a stored data at the particular block.

18. The non-transitory computer-readable storage medium of claim 15 , wherein adding the particular block to the first pool of blocks comprises:

erasing data stored at the particular block from the second pool of blocks; and

adding the particular block to the first pool of blocks in response to erasing the data.

19. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is to perform operations further comprising:

receiving user data;

generating system data of a memory sub-system associated with the memory device;

storing the user data to a block from the second pool of blocks at the plurality of bits per memory cell; and

storing the system data to a block from the first pool of blocks at the single bit per memory cell.

20. The non-transitory computer-readable storage medium of claim 19 , wherein the system data corresponds to a characteristic of the memory sub-system at a time when the user data is stored at the memory sub-system.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2022
From: AWUSIE, ROLAND J
To: MICRON TECHNOLOGY, INC.
Reel/Frame 059894/0597 →
Continuity (3)
Continuation 16924938 · Jul 9, 2020
Division 16228387 · Dec 20, 2018
Related Publication 20220254436A1 · Aug 11, 2022