Multi-die, vertical-wire package-in-package apparatus, and methods of making same
A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package.
1. A package-in-package apparatus comprising:
a first memory module coupled to a bond-wire board through a first vertical bond wire, a first redistribution layer and a first curved wire bond, wherein the first vertical bond wire includes a wire bond bead at a first end, and emerges from a first matrix at a second end;
a subsequent memory module disposed above the first memory module and coupled to the bond-wire board through a subsequent vertical bond wire, a subsequent redistribution layer and a subsequent curved wire bond, wherein the subsequent vertical bond wire emerges from a subsequent matrix; and
an encapsulation that covers the first and subsequent memory modules, the first and subsequent curved wire bonds, and a module side of the bond-wire board.
2. The memory apparatus of claim 1 , further including a second memory module stacked above and on the first memory module, and coupled to the bond-wire board through a second vertical bond wire, a second redistribution layer and a second curved wire bond, wherein the second vertical bond wire emerges from a second matrix.
3. The memory apparatus of claim 2 , further including a third memory module stacked below the subsequent memory module and above and on the second memory module, and coupled to the bond-wire board through a third vertical bond wire, a third redistribution layer and a third curved wire bond, wherein the third vertical bond wire emerges from a third matrix.
4. The memory apparatus of claim 1 , further including:
a second memory module stacked above and on the first memory module, and coupled to the bond-wire board through a second vertical bond wire, a second redistribution layer and a second curved wire bond, wherein the second vertical bond wire emerges from a second matrix;
a third memory module stacked below and on the subsequent memory module, and coupled to the bond-wire board through a third vertical bond wire, a third redistribution layer and a third curved wire bond, wherein the third vertical bond wire emerges from a third matrix; and
wherein the first and second memory modules are wire bonded with the first and second wire bonds, to a first edge of the bond-wire board, and wherein the third and subsequent memory modules are wire bonded with the third and subsequent curved wire bonds to an edge of the bond-wire board other than the first edge.
5. The package-in-package apparatus of claim 4 , wherein the second memory module is stair-step stacked on the first memory module, and wherein the subsequent memory module is stair-step stacked on the third memory module.
6. The package-in-package apparatus of claim 5 , wherein the first memory module includes four NAND memory dice, the second memory module includes four NAND memory dice, the third memory module includes four NAND memory dice, the subsequent memory module includes four NAND memory dice, and wherein each memory die is coupled to a corresponding redistribution layer by a vertical bond wire.
7. The package-in-package apparatus of claim 1 , further:
wherein the first memory module includes a first plurality of stacked memory dice coupled to the first redistribution layer by a first plurality of vertical bond wires; and
wherein the subsequent memory module includes a subsequent plurality of stacked memory dice coupled to the subsequent redistribution layer by a subsequent plurality of bond wires.
8. The package-in-package apparatus of claim 1 , further including:
a board onto which the bond-wire board is mounted at a land side that is opposite the module side, wherein the board is part of a computing system.
9. The package-in-package apparatus of claim 1 , wherein the first memory module vertical bond wire is arranged opposite to the subsequent memory module vertical bond wire.
10. A computing system, comprising:
a first memory module coupled to a bond-wire board through a first vertical bond wire, a first redistribution layer and a first curved wire bond, wherein the first vertical bond wire includes a wire bond bead at a first end, and emerges from a first matrix at a second end;
a second memory module stacked on the first memory module and coupled to the bond-wire board through a second vertical bond wire, a second redistribution layer and a second curved wire bond, wherein the second vertical bond wire emerges from a second matrix;
a third memory module stacked below the subsequent memory module and coupled to the bond-wire board through a third vertical bond wire, a third redistribution layer and a third curved wire bond, wherein the third vertical bond wire emerges from a third matrix;
a subsequent memory module coupled to the bond-wire board through a subsequent vertical bond wire, a subsequent redistribution layer and a subsequent curved wire bond, wherein the subsequent vertical bond wire emerges from a subsequent matrix;
an encapsulation that covers the first and subsequent memory modules, the first and subsequent curved wire bonds, and a module side of the bond-wire board;
wherein the first and second memory modules are wire bonded with the first and second wire bonds, to a first edge of the bond-wire board, and wherein the third and subsequent memory modules are wire bonded with the third and subsequent curved wire bonds to an edge of the bond-wire board other than the first edge; and
a board onto which the bond-wire board is mounted, wherein the board includes an external shell.
11. The computing system of claim 10 , further including a memory-controller hub disposed adjacent a first spacer, wherein the memory-controller hub is coupled to the first redistribution layer.
12. The computing system of claim 10 , wherein the computing system includes a chipset coupled to the first memory module.