Method for patterning a dielectric layer
A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.
1. A method for processing a substrate, the method comprising:
providing a substrate having a dielectric layer disposed over a semiconductor substrate layer;
forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer comprising a top portion and a bottom portion, wherein the patterned hard mask layer exposes a portion of a major surface of the dielectric layer, the bottom portion comprising a metal-containing hard mask material including titanium nitride, titanium, tantalum nitride, tantalum, ruthenium, tungsten based compounds, or aluminum-based compounds, and the top portion comprising a dielectric-containing hard mask material including silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, carbon doped silicon, or carbon doped silicon oxide;
performing a first timed etch process for a first etch time, the first timed etch process simultaneously removing a first portion of the dielectric layer and the top portion of the patterned hard mask layer; and
removing a second portion of the dielectric layer by performing a cyclic etch process comprising a plurality of cycles, wherein performing one cycle of the plurality of cycles comprises
forming a reconstructed portion of the patterned hard mask layer by performing an area selective deposition process, and
after forming the reconstructed portion of the hard mask layer, performing a second timed etch process for a second etch time, the second timed etch process removing material from the dielectric layer and the reconstructed portion.
2. The method of claim 1 , further comprising:
selecting a deposition thickness for the reconstructed portion of the hard mask layer; and
selecting the second etch time for the second timed etch process to etch 90% to 100% of the selected deposition thickness of the reconstructed portion of the hard mask layer.
3. A method for patterning a substrate, the method comprising:
providing a substrate having a dielectric layer disposed over a semiconductor substrate layer;
forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer, the patterned hard mask layer comprising a top portion and a bottom portion, the bottom portion comprising a metal-containing hard mask material including titanium nitride, titanium, tantalum nitride, tantalum, ruthenium, tungsten based compounds, or aluminum based compounds, and the top portion comprising a dielectric-containing hard mask material including silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, carbon doped silicon, or carbon doped silicon oxide; and
performing a concurrent deposition and etch process to remove a portion of the dielectric layer, the concurrent deposition and etch process comprising
removing material from the dielectric layer, and
selectively coating the patterned hard mask layer with hard mask material by selectively depositing material formed from the removing.
4. The method of claim 3 , wherein the selectively coating the patterned hard mask layer comprises selectively depositing material with sputtering.
5. The method of claim 3 , wherein the selectively coating the patterned hard mask layer comprises selectively depositing material by exposing the substrate to a precursor gas.
6. The method of claim 3 , further comprising:
prior to performing the concurrent deposition and etch process, performing a timed etch process for a selected etch time, the timed etch process simultaneously removing a portion of the dielectric layer and a top portion of the patterned hard mask layer, wherein the patterned hard mask layer comprises the top portion and a bottom portion underlying the top portion.