Stacked via structure disposed on a conductive pillar of a semiconductor die
A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
1. A stacked via structure, disposed on a conductive pillar of a semiconductor die, the stacked via structure comprising:
a first dielectric layer covering the semiconductor die;
a first conductive via embedded in the first dielectric layer, wherein the first conductive via is electrically and physically connected to the conductive pillar of the semiconductor die;
a first redistribution wiring covering a top surface of the first conductive via and a top surface of the first dielectric layer;
a second dielectric layer covering the first dielectric layer and the first redistribution wiring;
a second conductive via embedded in the second dielectric layer, wherein the second conductive via is landed on and in physical contact with the first redistribution wiring; and
a second redistribution wiring covering a top surface of the second conductive via and a top surface of the second dielectric layer, wherein a first lateral dimension of the first conductive via is greater than a second lateral dimension of the second conductive via.
2. The stacked via structure as claimed in claim 1 further comprising:
a third dielectric layer covering the second dielectric layer and the second redistribution wiring;
a third conductive via embedded in the third dielectric layer and landed on the second redistribution wiring; and
a third redistribution wiring covering a top surface of the third conductive via and a top surface of the third dielectric layer.
3. The stacked via structure as claimed in claim 2 , wherein the second lateral dimension of the second conductive via is greater than a third lateral dimension of the third conductive via.
4. The stacked via structure as claimed in claim 2 , wherein the second lateral dimension of the second conductive via is equal to a third lateral dimension of the third conductive via.
5. The stacked via structure as claimed in claim 2 further comprising:
a fourth dielectric layer covering the third dielectric layer and the third redistribution wiring;
a fourth conductive via embedded in the fourth dielectric layer and landed on the third redistribution wiring; and
a fourth redistribution wiring covering a top surface of the fourth conductive via and a top surface of the fourth dielectric layer.
6. The stacked via structure as claimed in claim 5 , wherein the third lateral dimension of the third conductive via is greater than a fourth lateral dimension of the fourth conductive via.
7. The stacked via structure as claimed in claim 5 , wherein the third lateral dimension of the third conductive via is equal to a fourth lateral dimension of the fourth conductive via.
8. The stacked via structure as claimed in claim 1 , wherein the first conductive via comprises first tapered sidewalls, and the second conductive via comprises second tapered sidewalls.
9. The stacked via structure as claimed in claim 1 , wherein the first conductive via comprises first vertical sidewalls, and the second conductive via comprises second vertical sidewalls.
10. The stacked via structure as claimed in claim 1 , wherein a first centerline of the first conductive via is aligned with a second centerline of the second conductive via.
11. The stacked via structure as claimed in claim 1 , wherein a first centerline of the first conductive via is offset from a second centerline of the second conductive via.
12. A stacked via structure, disposed on a conductive pillar of a semiconductor die, the stacked via structure comprising:
a first dielectric layer covering the semiconductor die;
a first conductive via embedded in the first dielectric layer, wherein the first conductive via is landed on and in physical contact with the conductive pillar of the semiconductor die;
a first redistribution wiring covering a top surface of the first conductive via and a top surface of the first dielectric layer;
a second dielectric layer covering the first dielectric layer and the first redistribution wiring;
a second conductive via embedded in the second dielectric layer, wherein the second conductive via is landed on and in physical contact with the first redistribution wiring; and
a second redistribution wiring covering a top surface of the second conductive via and a top surface of the second dielectric layer, wherein a first contact area of the first conductive via and the conductive pillar is greater than a second contact area of the second conductive via and the first redistribution wiring.
13. The stacked via structure as claimed in claim 12 further comprising:
a third dielectric layer covering the second dielectric layer and the second redistribution wiring;
a third conductive via embedded in the third dielectric layer and landed on the second redistribution wiring; and
a third redistribution wiring covering a top surface of the third conductive via and a top surface of the third dielectric layer, wherein the second contact area is greater than or equal to a third contact area of the third conductive via and the second redistribution wiring.
14. The stacked via structure as claimed in claim 13 further comprising:
a fourth dielectric layer covering the third dielectric layer and the third redistribution wiring;
a fourth conductive via embedded in the fourth dielectric layer and landed on the third redistribution wiring; and
a fourth redistribution wiring covering a top surface of the fourth conductive via and a top surface of the fourth dielectric layer, wherein the third contact area is greater than or equal to a fourth contact area of the fourth conductive via and the third redistribution wiring.
15. The stacked via structure as claimed in claim 12 , wherein the first conductive via comprises tapered sidewalls or vertical sidewalls, and the second conductive via comprises tapered sidewalls or vertical sidewalls.
16. The stacked via structure as claimed in claim 12 , wherein a first centerline of the first conductive via is aligned with a second centerline of the second conductive via.
17. The stacked via structure as claimed in claim 12 , wherein a first centerline of the first conductive via is offset from a second centerline of the second conductive via.
18. A structure, comprising:
a semiconductor die comprising conductive terminals;
conductive through vias disposed aside the semiconductor die;
an insulating encapsulation laterally encapsulating the semiconductor die and the conductive through vias;
a redistribution circuit structure, comprising:
stacked dielectric layers covering the semiconductor die and the insulating encapsulation;
a first conductive via embedded in a bottommost dielectric layer among the stacked dielectric layers, wherein the first conductive via is electrically and physically connected to at least one of the conductive terminals or the conductive through vias;
a first redistribution wiring covering a top surface of the first conductive via and a top surface of the first dielectric layer;
a second conductive via embedded in an upper dielectric layer among the stacked dielectric layers, wherein the second conductive via is landed on and in physical contact with the first redistribution wiring; and
a second redistribution wiring covering a top surface of the second conductive via, wherein a first lateral dimension of the first conductive via is greater than a second lateral dimension of the second conductive via.
19. The structure as claimed in claim 18 , wherein a first centerline of the first conductive via is offset from a second centerline of the second conductive via.
20. The structure as claimed in claim 18 , wherein a first centerline of the first conductive via is aligned with a second centerline of the second conductive via.