Common-connection method in 3D memory

1. A semiconductor device comprising:

a first drain/source structure extending in a first direction;

a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction;

a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction;

a first bit line extending in a third direction perpendicular to the first direction and the second direction, the first bit line disposed over the first drain/source structure in the first direction;

a common select line that includes a portion extending in the third direction and disposed over the second drain/source structure in the first direction;

a second bit line extending in the third direction and disposed over the third drain/source structure in the first direction;

a charge storage layer having at least a portion continuously extending along the second direction to couple to a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure; and

a channel that is interposed between the charge storage layer and the at least first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.

2. The semiconductor device of claim 1 , wherein the charge storage layer wraps around the first drain/source structure, the second drain/source structure, and the third drain/source structure.

3. The semiconductor device of claim 1 , further comprising a second charge storage layer having at least a portion continuously extending along the second direction to couple to a second sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.

4. The semiconductor device of claim 1 , further comprising a gate structure coupled to the charge storage layer.

5. The semiconductor device of claim 4 , wherein the gate structure wraps around the charge storage layer.

6. The semiconductor device of claim 1 , further comprising:

a fourth drain/source structure spaced from the first drain/source structure in the third direction;

a fifth drain/source structure spaced from the fourth drain/source structure in the second direction;

a sixth drain/source structure spaced from the fifth drain/source structure in the second direction; and

a second charge storage layer coupled to at least a second sidewall of each of the fourth drain/source structure, the fifth drain/source structure, and the sixth drain/source structure.

7. The semiconductor device of claim 6 , wherein the portion of the common select line is disposed over the fifth drain/source structure in the first direction.

8. The semiconductor device of claim 6 , further comprising:

a third bit line extending in the and disposed over the fourth drain/source structure in the first direction; and

a fourth bit line extending in the third direction and disposed over the sixth drain/source structure in the first direction.

9. The semiconductor device of claim 6 , further comprising a gate structure coupled between the charge storage layer and the second charge storage layer.

10. The semiconductor device of claim 6 , further comprising a gate structure that wraps around the charge storage layer and the second charge storage layer.

11. A semiconductor device, comprising:

a first metal structure extending in a vertical direction;

a second metal structure extending in the vertical direction and spaced from the first metal structure in a first lateral direction;

a third metal structure extending in the vertical direction and interposed between the first metal structure and the second metal structure in the first lateral direction;

a first charge storage layer having at least a portion continuously extending along the first lateral direction that is coupled to a first sidewall of each of the first metal structure, the second metal structure, and the third metal structure; and

a channel that is interposed between the first charge storage layer and the first sidewall of each of the first metal structure, the second metal structure, and the third metal structure.

12. The semiconductor device of claim 11 , further comprising:

a first bit line extending in a second lateral direction perpendicular to the first lateral direction, disposed over the first to third metal structures, and in connection with the first metal structure;

a common select line that includes a portion extending in the second lateral direction, disposed over the first to third metal structures, and in connection with the third metal structure; and

a second bit line extending in the second lateral direction, disposed over the first to third metal structures, and in connection with the second metal structure.

13. The semiconductor device of claim 11 , wherein the first to third metal structures are aligned along the first lateral direction, with the first charge storage layer fully surrounding the first to third metal structures.

14. The semiconductor device of claim 13 , further comprising:

a plurality of word lines spaced from one another in the vertical direction;

wherein each of the plurality of word lines fully surrounds the first charge storage layer.

15. The semiconductor device of claim 11 , further comprising:

a second charge storage layer having at least a portion continuously extending along the first lateral direction that is coupled to a second sidewall of each of the first metal structure, the second metal structure, and the third metal structure;

wherein the first sidewall and the second sidewall are opposite to each other.

16. The semiconductor device of claim 14 , wherein the first and second charge storage layers are each formed of a ferroelectric material.

17. The semiconductor device of claim 15 , further comprising:

a plurality of first word lines spaced from one another in the vertical direction, wherein each of the plurality of first word lines faces the first sidewall of each of the first to third metal structures; and

a plurality of second word lines spaced from one another in the vertical direction, wherein each of the plurality of second word lines faces the second sidewall of each of the first to third metal structures.

18. A semiconductor device, comprising:

a first metal structure extending in a vertical direction;

a second metal structure extending in the vertical direction and spaced from the first metal structure in a first lateral direction;

a third metal structure extending in the vertical direction and interposed between the first metal structure and the second metal structure in the first lateral direction;

a first semiconductor channel layer having at least a portion continuously extending along the first lateral direction that is in direct contact with a first sidewall of each of the first metal structure, the second metal structure, and the third metal structure; and

a first charge storage layer having at least a portion continuously extending along the first lateral direction that is in direct contact with the portion of the first semiconductor channel layer.

19. The semiconductor device of claim 18 , further comprising:

a second semiconductor channel layer having at least a portion continuously extending along the first lateral direction that is in direct contact with a second sidewall of each of the first metal structure, the second metal structure, and the third metal structure; and

a second charge storage layer having at least a portion continuously extending along the first lateral direction that is in direct contact with the portion of the second semiconductor channel layer;

wherein the first and second sidewalls are opposite to each other.